diff --git a/cores/archie/fpga/mist/archimedes_mist_top.qsf b/cores/archie/fpga/mist/archimedes_mist_top.qsf index 96b2512..db7c9bf 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.qsf +++ b/cores/archie/fpga/mist/archimedes_mist_top.qsf @@ -226,4 +226,5 @@ set_global_assignment -name QIP_FILE rom_reconfig_36.qip set_global_assignment -name QIP_FILE pll_vidc.qip set_global_assignment -name SIGNALTAP_FILE output_files/vidc.stp set_global_assignment -name SIGNALTAP_FILE output_files/sd.stp +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/cores/archie/fpga/mist/archimedes_mist_top.sdc b/cores/archie/fpga/mist/archimedes_mist_top.sdc index 989ffa9..c1ade17 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.sdc +++ b/cores/archie/fpga/mist/archimedes_mist_top.sdc @@ -100,8 +100,8 @@ set_false_path -to [get_ports {LED}] # Set Multicycle Path #************************************************************** -set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -setup 4 -set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -hold 3 +set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -setup 3 +set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -hold 2 set_multicycle_path -to {VGA_*[*]} -setup 4 set_multicycle_path -to {VGA_*[*]} -hold 3 diff --git a/cores/archie/fpga/mist/archimedes_mist_top.v b/cores/archie/fpga/mist/archimedes_mist_top.v index 3718d4d..f46071f 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.v +++ b/cores/archie/fpga/mist/archimedes_mist_top.v @@ -67,8 +67,8 @@ wire kbd_in_strobe; // generated clocks wire clk_pix; wire ce_pix; -wire clk_32m /* synthesis keep */ ; -wire clk_128m /* synthesis keep */ ; +wire clk_sys /* synthesis keep */ ; +wire clk_mem /* synthesis keep */ ; //wire clk_8m /* synthesis keep */ ; wire pll_ready; @@ -106,9 +106,8 @@ wire ypbpr; clockgen CLOCKS( .inclk0 (CLOCK_27[0]), - .c0 (clk_32m), - .c1 (clk_128m), -// .c2 (clk_50m), + .c0 (clk_sys), // 40 MHz + .c1 (clk_mem), // 120 MHz .c3 (DRAM_CLK), .locked (pll_ready) // pll locked output ); @@ -147,7 +146,7 @@ wire q_reconfig_36; rom_reconfig_25 rom_reconfig_25 ( .address(pll_rom_address), - .clock(clk_32m), + .clock(clk_sys), .rden(pll_write_rom_ena), .q(q_reconfig_25) ); @@ -155,7 +154,7 @@ rom_reconfig_25 rom_reconfig_25 rom_reconfig_24 rom_reconfig_24 ( .address(pll_rom_address), - .clock(clk_32m), + .clock(clk_sys), .rden(pll_write_rom_ena), .q(q_reconfig_24) ); @@ -163,7 +162,7 @@ rom_reconfig_24 rom_reconfig_24 rom_reconfig_36 rom_reconfig_36 ( .address(pll_rom_address), - .clock(clk_32m), + .clock(clk_sys), .rden(pll_write_rom_ena), .q(q_reconfig_36) ); @@ -174,7 +173,7 @@ assign pll_rom_q = pixbaseclk_select == 2'b01 ? q_reconfig_25 : pll_reconfig pll_reconfig_inst ( .busy(pll_reconfig_busy), - .clock(clk_32m), + .clock(clk_sys), .counter_param(0), .counter_type(0), .data_in(0), @@ -197,7 +196,7 @@ pll_reconfig pll_reconfig_inst .write_rom_ena(pll_write_rom_ena) ); -always @(posedge clk_32m) begin +always @(posedge clk_sys) begin reg [1:0] pixbaseclk_select_d; reg [1:0] pll_reconfig_state = 0; reg [9:0] pll_reconfig_timeout; @@ -296,7 +295,7 @@ assign SPI_DO = (CONF_DATA0==0)?user_io_sdo:1'bZ; wire user_io_sdo; user_io user_io( // the spi interface - .clk_sys ( clk_32m ), + .clk_sys ( clk_sys ), .SPI_CLK (SPI_SCK ), .SPI_SS_IO (CONF_DATA0 ), .SPI_MISO (user_io_sdo ), // tristate handling inside user_io @@ -342,7 +341,7 @@ DATA_IO ( .index ( dio_index ), // ram interface - .clk ( clk_32m ), + .clk ( clk_sys ), .wr ( loader_we ), .a ( loader_addr ), .sel ( loader_sel ), @@ -366,7 +365,7 @@ wire i2c_din, i2c_dout, i2c_clock; archimedes_top ARCHIMEDES( - .CLKCPU_I ( clk_32m ), + .CLKCPU_I ( clk_sys ), .CLKPIX_I ( clk_pix ), // pixel clock for OSD .CEPIX_O ( ce_pix ), @@ -432,7 +431,7 @@ wire [25:0] ram_address/* synthesis keep */ ; sdram_top SDRAM( // wishbone interface - .wb_clk ( clk_32m ), + .wb_clk ( clk_sys ), .wb_stb ( ram_stb ), .wb_cyc ( ram_cyc ), .wb_we ( ram_we ), @@ -445,7 +444,7 @@ sdram_top SDRAM( .wb_cti ( core_cti_o ), // SDRAM Interface - .sd_clk ( clk_128m ), + .sd_clk ( clk_mem ), .sd_rst ( ~pll_ready ), .sd_cke ( DRAM_CKE ), @@ -461,7 +460,7 @@ sdram_top SDRAM( ); i2cSlaveTop CMOS ( - .clk ( clk_32m ), + .clk ( clk_sys ), .rst ( ~pll_ready ), .sdaIn ( i2c_din ), .sdaOut ( i2c_dout ), @@ -480,7 +479,7 @@ audio AUDIO ( .audio_r ( AUDIO_R ) ); -always @(posedge clk_32m) begin +always @(posedge clk_sys) begin reg loader_active_old; loader_active_old <= loader_active; diff --git a/cores/archie/fpga/mist/clockgen.v b/cores/archie/fpga/mist/clockgen.v index a447299..9bf424b 100644 --- a/cores/archie/fpga/mist/clockgen.v +++ b/cores/archie/fpga/mist/clockgen.v @@ -111,17 +111,17 @@ module clockgen ( .vcounderrange ()); defparam altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 27, + altpll_component.clk0_divide_by = 9, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 32, + altpll_component.clk0_multiply_by = 14, altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 27, + altpll_component.clk1_divide_by = 3, altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 128, + altpll_component.clk1_multiply_by = 14, altpll_component.clk1_phase_shift = "0", - altpll_component.clk3_divide_by = 27, + altpll_component.clk3_divide_by = 3, altpll_component.clk3_duty_cycle = 50, - altpll_component.clk3_multiply_by = 128, + altpll_component.clk3_multiply_by = 14, altpll_component.clk3_phase_shift = "-1845", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, @@ -202,9 +202,9 @@ endmodule // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "128.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "128.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "42.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "126.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "126.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -235,9 +235,9 @@ endmodule // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "128.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "128.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "42.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "126.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "126.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1" @@ -263,6 +263,7 @@ endmodule // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clockgen.mif" // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" @@ -289,17 +290,17 @@ endmodule // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "14" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "128" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "14" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "3" // Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "128" +// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "14" // Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-1845" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" @@ -371,6 +372,5 @@ endmodule // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_inst.v FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_bb.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.mif FALSE // Retrieval info: LIB_FILE: altera_mf // Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/cores/archie/rtl/fdc1772.v b/cores/archie/rtl/fdc1772.v index 269fc83..e94853c 100644 --- a/cores/archie/rtl/fdc1772.v +++ b/cores/archie/rtl/fdc1772.v @@ -62,7 +62,7 @@ module fdc1772 ( input sd_din_strobe ); -localparam CLK = 32000000; +localparam CLK = 42000000; localparam CLK_EN = 8000000; // ------------------------------------------------------------------------- diff --git a/cores/archie/rtl/ioc.v b/cores/archie/rtl/ioc.v index 6dc8f25..33d01c0 100644 --- a/cores/archie/rtl/ioc.v +++ b/cores/archie/rtl/ioc.v @@ -69,8 +69,7 @@ module ioc( input kbd_in_strobe ); -reg [3:0] clk2m_count; -reg [1:0] clk8m_count; +reg [4:0] clken_counter; wire [7:0] irqa_dout, irqb_dout, firq_dout; wire irqa_req, irqb_req, firq_req; @@ -229,9 +228,6 @@ initial begin ctrl_state = 6'h3F; - clk8m_count = 'd0; - clk2m_count = 'd0; - ir_r = 1'b1; end @@ -253,10 +249,10 @@ always @(posedge clkcpu) begin end - // increment the clock counters. - clk2m_count <= clk2m_count + 1'd1; - clk8m_count <= clk8m_count + 1'd1; - + // increment the clock counter. 42 MHz clkcpu assumed. + clken_counter <= clken_counter + 1'd1; + if (clken_counter == 20) clken_counter <= 0; + if (write_request & ctrl_selected) begin ctrl_state <= wb_dat_i[5:0]; @@ -288,9 +284,8 @@ assign ctrl_dout = { ir, 1'b1, c_in & c_out }; assign ir_edge = ~ir_r & ir; -// pulse the 2mhz & 8mhz clock enable line high when all the bits are set. -assign clk2m_en = &clk2m_count; -assign clk8m_en = &clk8m_count; +assign clk2m_en = !clken_counter; +assign clk8m_en = clken_counter == 0 || clken_counter == 5 || clken_counter == 10 || clken_counter == 15; assign wb_dat_o = read_request ? (ctrl_selected ? ctrl_dout :