From dd9e4003348de8996ae2c3dfc034e4e27490e7a5 Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Sat, 9 Feb 2019 01:20:29 +0100 Subject: [PATCH] [Archie] Adjust SDRAM timings --- .../archie/fpga/mist/archimedes_mist_top.qsf | 19 ++- .../archie/fpga/mist/archimedes_mist_top.sdc | 123 ++++++++++++++++++ cores/archie/fpga/mist/archimedes_mist_top.v | 3 +- cores/archie/fpga/mist/clockgen.ppf | 1 + cores/archie/fpga/mist/clockgen.v | 54 ++++++-- cores/archie/fpga/mist/clockgen_bb.v | 24 +++- cores/archie/rtl/sdram/sdram_defines.v | 2 +- cores/archie/rtl/sdram/sdram_init.v | 18 +-- cores/archie/rtl/sdram/sdram_top.v | 21 +-- 9 files changed, 219 insertions(+), 46 deletions(-) create mode 100644 cores/archie/fpga/mist/archimedes_mist_top.sdc diff --git a/cores/archie/fpga/mist/archimedes_mist_top.qsf b/cores/archie/fpga/mist/archimedes_mist_top.qsf index 13ff745..6d45b2e 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.qsf +++ b/cores/archie/fpga/mist/archimedes_mist_top.qsf @@ -131,7 +131,12 @@ set_location_assignment PIN_43 -to DRAM_CLK set_location_assignment PIN_65 -to AUDIO_L set_location_assignment PIN_80 -to AUDIO_R -set_global_assignment -name ENABLE_SIGNALTAP ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DRAM_* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_* +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_* + +set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE signal_tap.stp set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF @@ -203,4 +208,16 @@ set_global_assignment -name CDF_FILE Chain2.cdf set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_top.v set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_init.v set_global_assignment -name QIP_FILE clockdivide.qip +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/cores/archie/fpga/mist/archimedes_mist_top.sdc b/cores/archie/fpga/mist/archimedes_mist_top.sdc new file mode 100644 index 0000000..bd7f196 --- /dev/null +++ b/cores/archie/fpga/mist/archimedes_mist_top.sdc @@ -0,0 +1,123 @@ +## Generated SDC file "hello_led.out.sdc" + +## Copyright (C) 1991-2011 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition" + +## DATE "Fri Jul 06 23:05:47 2012" + +## +## DEVICE "EP3C25Q240C8" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name clk_27 -period 37.037 [get_ports {CLOCK_27[0]}] +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +#************************************************************** +# Create Generated Clock +#************************************************************** + +derive_pll_clocks + +#************************************************************** +# Set Clock Latency +#************************************************************** + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +derive_clock_uncertainty; + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -max 6.4 [get_ports DRAM_DQ[*]] +set_input_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -min 3.2 [get_ports DRAM_DQ[*]] + + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -max 1.5 [get_ports {DRAM_D* DRAM_A* DRAM_BA* DRAM_n* DRAM_CKE}] +set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -min -0.8 [get_ports {DRAM_D* DRAM_A* DRAM_BA* DRAM_n* DRAM_CKE}] +set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[3]}] -max 1.5 [get_ports DRAM_CLK] +set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[3]}] -min -0.8 [get_ports DRAM_CLK] + +set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[2]}] -max 0 [get_ports {VGA_*}] +set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[2]}] -min -5 [get_ports {VGA_*}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {CLOCKS|*}] +set_clock_groups -asynchronous -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[2]}] +set_clock_groups -asynchronous -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[2]}] + +#************************************************************** +# Set False Path +#************************************************************** + +#set_false_path -to [get_ports {VGA_*}] +set_false_path -to [get_ports {UART_TX}] +set_false_path -to [get_ports {AUDIO_L}] +set_false_path -to [get_ports {AUDIO_R}] +set_false_path -to [get_ports {LED}] + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -setup 4 +set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -hold 3 + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** diff --git a/cores/archie/fpga/mist/archimedes_mist_top.v b/cores/archie/fpga/mist/archimedes_mist_top.v index 048a046..94b8c3d 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.v +++ b/cores/archie/fpga/mist/archimedes_mist_top.v @@ -105,6 +105,7 @@ clockgen CLOCKS( .c0 (clk_32m), .c1 (clk_128m), .c2 (clk_50m), + .c3 (DRAM_CLK), .locked (pll_ready) // pll locked output ); @@ -324,6 +325,4 @@ assign ram_cyc = loader_active ? loader_stb : core_stb_out; assign ram_data_in = loader_active ? loader_data : core_data_out; assign core_ack_in = loader_active ? 1'b0 : ram_ack; -assign DRAM_CLK = clk_128m; - endmodule // archimedes_papoliopro_top diff --git a/cores/archie/fpga/mist/clockgen.ppf b/cores/archie/fpga/mist/clockgen.ppf index f8f6ae0..1805ae9 100644 --- a/cores/archie/fpga/mist/clockgen.ppf +++ b/cores/archie/fpga/mist/clockgen.ppf @@ -6,6 +6,7 @@ + diff --git a/cores/archie/fpga/mist/clockgen.v b/cores/archie/fpga/mist/clockgen.v index 6267431..eb61664 100644 --- a/cores/archie/fpga/mist/clockgen.v +++ b/cores/archie/fpga/mist/clockgen.v @@ -41,31 +41,35 @@ module clockgen ( c0, c1, c2, + c3, locked); input inclk0; output c0; output c1; output c2; + output c3; output locked; wire [4:0] sub_wire0; - wire sub_wire2; - wire [0:0] sub_wire7 = 1'h0; - wire [2:2] sub_wire4 = sub_wire0[2:2]; - wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire sub_wire3; + wire [0:0] sub_wire8 = 1'h0; + wire [2:2] sub_wire5 = sub_wire0[2:2]; + wire [0:0] sub_wire4 = sub_wire0[0:0]; + wire [3:3] sub_wire2 = sub_wire0[3:3]; wire [1:1] sub_wire1 = sub_wire0[1:1]; wire c1 = sub_wire1; - wire locked = sub_wire2; - wire c0 = sub_wire3; - wire c2 = sub_wire4; - wire sub_wire5 = inclk0; - wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + wire c3 = sub_wire2; + wire locked = sub_wire3; + wire c0 = sub_wire4; + wire c2 = sub_wire5; + wire sub_wire6 = inclk0; + wire [1:0] sub_wire7 = {sub_wire8, sub_wire6}; altpll altpll_component ( - .inclk (sub_wire6), + .inclk (sub_wire7), .clk (sub_wire0), - .locked (sub_wire2), + .locked (sub_wire3), .activeclock (), .areset (1'b0), .clkbad (), @@ -114,6 +118,10 @@ module clockgen ( altpll_component.clk2_duty_cycle = 50, altpll_component.clk2_multiply_by = 167, altpll_component.clk2_phase_shift = "0", + altpll_component.clk3_divide_by = 27, + altpll_component.clk3_duty_cycle = 50, + altpll_component.clk3_multiply_by = 128, + altpll_component.clk3_phase_shift = "-3700", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -149,7 +157,7 @@ module clockgen ( altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", altpll_component.port_clk2 = "PORT_USED", - altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_USED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", altpll_component.port_clkena0 = "PORT_UNUSED", @@ -190,12 +198,15 @@ endmodule // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "128.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.099998" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "128.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -218,32 +229,40 @@ endmodule // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "128.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "50.10000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "128.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-3700.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -268,15 +287,18 @@ endmodule // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLK3 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -293,6 +315,10 @@ endmodule // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "167" // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "128" +// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-3700" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -327,7 +353,7 @@ endmodule // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" @@ -346,6 +372,7 @@ endmodule // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 @@ -353,6 +380,7 @@ endmodule // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.ppf TRUE diff --git a/cores/archie/fpga/mist/clockgen_bb.v b/cores/archie/fpga/mist/clockgen_bb.v index 317b215..3ddac6e 100644 --- a/cores/archie/fpga/mist/clockgen_bb.v +++ b/cores/archie/fpga/mist/clockgen_bb.v @@ -36,12 +36,14 @@ module clockgen ( c0, c1, c2, + c3, locked); input inclk0; output c0; output c1; output c2; + output c3; output locked; endmodule @@ -68,12 +70,15 @@ endmodule // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "128.000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.099998" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "128.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -96,32 +101,40 @@ endmodule // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "128.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "50.10000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "128.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-3700.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -146,15 +159,18 @@ endmodule // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLK3 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -171,6 +187,10 @@ endmodule // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "167" // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27" +// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "128" +// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-3700" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -205,7 +225,7 @@ endmodule // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" @@ -224,6 +244,7 @@ endmodule // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 @@ -231,6 +252,7 @@ endmodule // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.ppf TRUE diff --git a/cores/archie/rtl/sdram/sdram_defines.v b/cores/archie/rtl/sdram/sdram_defines.v index f931b79..58bfc2e 100644 --- a/cores/archie/rtl/sdram/sdram_defines.v +++ b/cores/archie/rtl/sdram/sdram_defines.v @@ -29,7 +29,7 @@ localparam RASCAS_DELAY = 3'd3; // tRCD=20ns -> 3 cycles@128MHz localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8, 111 = continuous. localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved -localparam CAS_LATENCY = 3'd2; // 2/3 allowed +localparam CAS_LATENCY = 3'd3; // 2/3 allowed localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write localparam WRITE_BURST = 1'b0; // 0= write burst enabled, 1=only single access write diff --git a/cores/archie/rtl/sdram/sdram_init.v b/cores/archie/rtl/sdram/sdram_init.v index 73957da..092d04f 100644 --- a/cores/archie/rtl/sdram/sdram_init.v +++ b/cores/archie/rtl/sdram/sdram_init.v @@ -34,7 +34,7 @@ module sdram_init( input sd_rst, output reg [3:0] sd_cmd, output reg [12:0] sd_a, // 13 bit multiplexed address bus - output sd_rdy + output reg sd_rdy ); `include "sdram_defines.v" @@ -49,8 +49,8 @@ initial begin t = 4'd0; reset = 5'h1f; sd_a = 13'd0; - sd_cmd = CMD_INHIBIT; - + sd_cmd = CMD_INHIBIT; + sd_rdy = 0; end always @(posedge sd_clk) begin @@ -62,11 +62,12 @@ always @(posedge sd_clk) begin t <= 4'd0; reset <= 5'h1f; sd_a <= 13'd0; + sd_rdy <= 0; - end else if (!sd_rdy) begin + end else begin - t <= t + 4'd1; - + if (!sd_rdy) t <= t + 4'd1; + if (t ==4'hF) begin reset <= reset - 5'd1; end @@ -89,13 +90,12 @@ always @(posedge sd_clk) begin sd_cmd <= CMD_LOAD_MODE; sd_a <= MODE; end - + + if(reset == 0) sd_rdy <= 1; end end end -assign sd_rdy = reset == 5'd0; - endmodule \ No newline at end of file diff --git a/cores/archie/rtl/sdram/sdram_top.v b/cores/archie/rtl/sdram/sdram_top.v index ec00d48..72cefe8 100644 --- a/cores/archie/rtl/sdram/sdram_top.v +++ b/cores/archie/rtl/sdram/sdram_top.v @@ -32,7 +32,7 @@ module sdram_top ( input sd_clk, // sdram is accessed at 128MHz input sd_rst, // reset the sdram controller. output sd_cke, // clock enable. - inout [15:0] sd_dq, // 16 bit bidirectional data bus + inout [15:0] sd_dq, // 16 bit bidirectional data bus output [12:0] sd_addr, // 13 bit multiplexed address bus output reg[1:0] sd_dqm = 2'b00, // two byte masks output reg[1:0] sd_ba = 2'b00, // two banks @@ -111,7 +111,7 @@ localparam CYCLE_CAS0 = CYCLE_RFSH_START + RASCAS_DELAY; localparam CYCLE_CAS1 = CYCLE_CAS0 + 4'd1; localparam CYCLE_CAS2 = CYCLE_CAS1 + 4'd1; localparam CYCLE_CAS3 = CYCLE_CAS2 + 4'd1; -localparam CYCLE_READ0 = CYCLE_CAS0 + CAS_LATENCY + 4'd2; +localparam CYCLE_READ0 = CYCLE_CAS0 + CAS_LATENCY + 4'd1; localparam CYCLE_READ1 = CYCLE_READ0+ 1'd1; localparam CYCLE_READ2 = CYCLE_READ1+ 1'd1; localparam CYCLE_READ3 = CYCLE_READ2+ 1'd1; @@ -130,8 +130,6 @@ always @(posedge sd_clk) begin sd_we <= wb_we; sd_cmd <= CMD_INHIBIT; - if (sd_ready) begin - if (wb_stb & wb_cyc & ~wb_ack) begin sd_stb <= wb_stb; @@ -349,21 +347,6 @@ always @(posedge sd_clk) begin sd_burst <= 1'b0; end - - end else begin - - - - sd_stb <= 1'b0; - sd_cyc <= 1'b0; - sd_burst <= 1'b0; - - sd_cycle <= 4'd0; - sd_done <= 1'b0; - - end - - end reg wb_burst;