From e12192463a217258da3979d79b99eefe93788ce0 Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Sat, 9 Feb 2019 01:45:35 +0100 Subject: [PATCH] [Archie] Add YPbPr --- .../archie/fpga/mist/archimedes_mist_top.qsf | 31 ++++++----- cores/archie/fpga/mist/archimedes_mist_top.v | 31 +++++++++-- cores/archie/fpga/mist/rgb2ypbpr.sv | 55 +++++++++++++++++++ cores/archie/fpga/mist/user_io.v | 2 + 4 files changed, 98 insertions(+), 21 deletions(-) create mode 100644 cores/archie/fpga/mist/rgb2ypbpr.sv diff --git a/cores/archie/fpga/mist/archimedes_mist_top.qsf b/cores/archie/fpga/mist/archimedes_mist_top.qsf index 6d45b2e..85d3690 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.qsf +++ b/cores/archie/fpga/mist/archimedes_mist_top.qsf @@ -161,8 +161,24 @@ set_global_assignment -name GENERATE_RBF_FILE ON set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF set_location_assignment PIN_7 -to LED set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv set_global_assignment -name VERILOG_FILE sigma_delta_dac.v set_global_assignment -name VERILOG_FILE audio.v +set_global_assignment -name VERILOG_FILE data_io.v +set_global_assignment -name VERILOG_FILE user_io.v +set_global_assignment -name VERILOG_FILE osd.v set_global_assignment -name VERILOG_FILE ../../rtl/fdc1772.v set_global_assignment -name VERILOG_FILE ../../rtl/vidc_divider.v set_global_assignment -name VERILOG_FILE ../../rtl/latches.v @@ -178,9 +194,6 @@ set_global_assignment -name VERILOG_FILE ../../rtl/ioc_irq.v set_global_assignment -name VERILOG_FILE ../../rtl/ioc.v set_global_assignment -name VERILOG_FILE ../../rtl/amber/a23_barrel_shift.v set_global_assignment -name VERILOG_FILE ../../rtl/memc_translator.v -set_global_assignment -name VERILOG_FILE data_io.v -set_global_assignment -name VERILOG_FILE user_io.v -set_global_assignment -name VERILOG_FILE osd.v set_global_assignment -name VERILOG_FILE ../../rtl/gdb/slgdb_debug.v set_global_assignment -name VERILOG_FILE ../../sw/testdata/screenbox.v set_global_assignment -name VERILOG_FILE ../../rtl/vidc_fifo.v @@ -208,16 +221,4 @@ set_global_assignment -name CDF_FILE Chain2.cdf set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_top.v set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_init.v set_global_assignment -name QIP_FILE clockdivide.qip -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/cores/archie/fpga/mist/archimedes_mist_top.v b/cores/archie/fpga/mist/archimedes_mist_top.v index 94b8c3d..236a2c3 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.v +++ b/cores/archie/fpga/mist/archimedes_mist_top.v @@ -96,7 +96,7 @@ wire [7:0] joyA; wire [7:0] joyB; wire [1:0] buttons; wire [1:0] switches; - +wire ypbpr; // the top file should generate the correct clocks for the machine @@ -109,6 +109,8 @@ clockgen CLOCKS( .locked (pll_ready) // pll locked output ); +wire [5:0] osd_r_o, osd_g_o, osd_b_o; + osd #(0,0,4) OSD ( .clk_sys ( clk_pix ), @@ -123,13 +125,29 @@ osd #(0,0,4) OSD ( .HSync ( core_hs ), .VSync ( core_vs ), - .R_out ( VGA_R ), - .G_out ( VGA_G ), - .B_out ( VGA_B ) + .R_out ( osd_r_o ), + .G_out ( osd_g_o ), + .B_out ( osd_b_o ) ); -assign VGA_HS = core_hs; -assign VGA_VS = core_vs; +wire [5:0] Y, Pb, Pr; + +rgb2ypbpr rgb2ypbpr +( + .red ( osd_r_o ), + .green ( osd_g_o ), + .blue ( osd_b_o ), + .y ( Y ), + .pb ( Pb ), + .pr ( Pr ) +); + +assign VGA_R = ypbpr?Pr:osd_r_o; +assign VGA_G = ypbpr? Y:osd_g_o; +assign VGA_B = ypbpr?Pb:osd_b_o; +wire CSync = ~(core_hs ^ core_vs); +assign VGA_HS = ypbpr ? CSync : core_hs; +assign VGA_VS = ypbpr? 1'b1 : core_vs; // de-multiplex spi outputs from user_io and data_io assign SPI_DO = (CONF_DATA0==0)?user_io_sdo:(SPI_SS2==0)?data_io_sdo:1'bZ; @@ -145,6 +163,7 @@ user_io user_io( .SWITCHES (switches ), .BUTTONS (buttons ), + .ypbpr (ypbpr ), .JOY0 (joyA ), .JOY1 (joyB ), diff --git a/cores/archie/fpga/mist/rgb2ypbpr.sv b/cores/archie/fpga/mist/rgb2ypbpr.sv new file mode 100644 index 0000000..1e1662e --- /dev/null +++ b/cores/archie/fpga/mist/rgb2ypbpr.sv @@ -0,0 +1,55 @@ +module rgb2ypbpr ( + input [5:0] red, + input [5:0] green, + input [5:0] blue, + + output [5:0] y, + output [5:0] pb, + output [5:0] pr +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y_i = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb_i = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr_i = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign pr = yuv_full[pr_i - 8'd16]; +assign y = yuv_full[y_i - 8'd16]; +assign pb = yuv_full[pb_i - 8'd16]; + +endmodule diff --git a/cores/archie/fpga/mist/user_io.v b/cores/archie/fpga/mist/user_io.v index 36424d2..c6c8e21 100644 --- a/cores/archie/fpga/mist/user_io.v +++ b/cores/archie/fpga/mist/user_io.v @@ -31,6 +31,7 @@ module user_io ( output [7:0] JOY0, output [7:0] JOY1, + output ypbpr, input [7:0] kbd_out_data, input kbd_out_strobe, @@ -59,6 +60,7 @@ assign JOY1 = joystick_1[7:0]; assign BUTTONS = but_sw[1:0]; assign SWITCHES = but_sw[3:2]; +assign ypbpr = but_sw[5]; // this variant of user_io is for the achie core (type == a6) only wire [7:0] core_type = 8'ha6; reg [7:0] spi_byte_out;