diff --git a/cores/c64/Fix-scandoubler-and-OSD.patch b/cores/c64/Fix-scandoubler-and-OSD.patch new file mode 100644 index 0000000..8deb88d --- /dev/null +++ b/cores/c64/Fix-scandoubler-and-OSD.patch @@ -0,0 +1,716 @@ +From 43d3e9878b5b1b7b9a194a4dd6e31aa9fbc58482 Mon Sep 17 00:00:00 2001 +From: sorgelig +Date: Sun, 10 Jan 2016 00:16:20 +0800 +Subject: [PATCH] Fix scandoubler and OSD. + +--- + mist/C64_mist.qsf | 1 + + mist/osd.v | 81 ++++++----------- + mist/scandoubler.v | 222 ++++++++++++++++++++++++++++++--------------- + rtl_dar/c64_mist.vhd | 86 ++++++++++++++---- + rtl_dar/composite_sync.vhd | 8 ++ + rtl_dar/fpga64_sid_iec.vhd | 79 ++-------------- + 6 files changed, 262 insertions(+), 215 deletions(-) + +diff --git a/mist/C64_mist.qsf b/mist/C64_mist.qsf +index 411f6a0..3e9ea6f 100644 +--- a/mist/C64_mist.qsf ++++ b/mist/C64_mist.qsf +@@ -61,6 +61,7 @@ set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" + set_global_assignment -name GENERATE_RBF_FILE ON + set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON + set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" ++set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + + set_location_assignment PIN_7 -to LED + set_location_assignment PIN_22 -to CLOCK_50[0] +diff --git a/mist/osd.v b/mist/osd.v +index a654b40..6e3fc29 100644 +--- a/mist/osd.v ++++ b/mist/osd.v +@@ -7,9 +7,9 @@ module osd ( + input pclk, + + // SPI interface +- input sck, +- input ss, +- input sdi, ++ input sck, ++ input ss, ++ input sdi, + + // VGA signals coming from core + input [5:0] red_in, +@@ -21,9 +21,7 @@ module osd ( + // VGA signals going to video connector + output [5:0] red_out, + output [5:0] green_out, +- output [5:0] blue_out, +- output hs_out, +- output vs_out ++ output [5:0] blue_out + ); + + parameter OSD_X_OFFSET = 10'd0; +@@ -89,8 +87,14 @@ reg [9:0] h_cnt; + reg hsD, hsD2; + reg [9:0] hs_low, hs_high; + wire hs_pol = hs_high < hs_low; +-wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high; +-wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] }; ++wire [9:0] dsp_width = hs_pol?hs_low:hs_high; ++ ++// vertical counter ++reg [9:0] v_cnt; ++reg vsD, vsD2; ++reg [9:0] vs_low, vs_high; ++wire vs_pol = vs_high < vs_low; ++wire [9:0] dsp_height = vs_pol?vs_low:vs_high; + + always @(posedge pclk) begin + // bring hsync into local clock domain +@@ -107,22 +111,13 @@ always @(posedge pclk) begin + else if(hsD && !hsD2) begin + h_cnt <= 10'd0; + hs_low <= h_cnt; ++ ++ v_cnt <= v_cnt + 10'd1; + end + + else + h_cnt <= h_cnt + 10'd1; +-end + +-// vertical counter +-reg [9:0] v_cnt; +-reg vsD, vsD2; +-reg [9:0] vs_low, vs_high; +-wire vs_pol = vs_high < vs_low; +-wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high; +-wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] }; +- +-always @(posedge hs_in) begin +- // bring vsync into local clock domain + vsD <= vs_in; + vsD2 <= vsD; + +@@ -137,46 +132,28 @@ always @(posedge hs_in) begin + v_cnt <= 10'd0; + vs_low <= v_cnt; + end +- +- else +- v_cnt <= v_cnt + 10'd1; + end + + // area in which OSD is being displayed +-wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1); +-wire [9:0] h_osd_end = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1; +-wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1); +-wire [9:0] v_osd_end = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1; +- +-reg h_osd_active, v_osd_active; +-always @(posedge pclk) begin +- if(hs_in != hs_pol) begin +- if(h_cnt == h_osd_start) h_osd_active <= 1'b1; +- if(h_cnt == h_osd_end) h_osd_active <= 1'b0; +- end +- if(vs_in != vs_pol) begin +- if(v_cnt == v_osd_start) v_osd_active <= 1'b1; +- if(v_cnt == v_osd_end) v_osd_active <= 1'b0; +- end +-end ++wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; ++wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; ++wire [9:0] v_osd_start = ((dsp_height- OSD_HEIGHT)>> 1) + OSD_Y_OFFSET; ++wire [9:0] v_osd_end = v_osd_start + OSD_HEIGHT; ++wire [9:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register ++wire [9:0] osd_vcnt = v_cnt - v_osd_start; + +-wire osd_de = osd_enable && h_osd_active && v_osd_active; ++wire osd_de = osd_enable && ++ (hs_in != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) && ++ (vs_in != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +-wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1; // one pixel offset for osd_byte register +-wire [6:0] osd_vcnt = v_cnt - v_osd_start; ++reg [7:0] osd_byte; ++always @(posedge pclk) osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt[7:0]}]; + + wire osd_pixel = osd_byte[osd_vcnt[3:1]]; +- +-reg [7:0] osd_byte; +-always @(posedge pclk) +- osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}]; +- + wire [2:0] osd_color = OSD_COLOR; +-assign red_out = !osd_de?red_in: {osd_pixel, osd_pixel, osd_color[2], red_in[5:3] }; +-assign green_out = !osd_de?green_in:{osd_pixel, osd_pixel, osd_color[1], green_in[5:3]}; +-assign blue_out = !osd_de?blue_in: {osd_pixel, osd_pixel, osd_color[0], blue_in[5:3] }; + +-assign hs_out = hs_in; +-assign vs_out = vs_in; ++assign red_out = !osd_de ? red_in : {osd_pixel, osd_pixel, osd_color[2], red_in[5:3] }; ++assign green_out = !osd_de ? green_in : {osd_pixel, osd_pixel, osd_color[1], green_in[5:3]}; ++assign blue_out = !osd_de ? blue_in : {osd_pixel, osd_pixel, osd_color[0], blue_in[5:3] }; + +-endmodule +\ No newline at end of file ++endmodule +diff --git a/mist/scandoubler.v b/mist/scandoubler.v +index 42bc596..5413b3e 100644 +--- a/mist/scandoubler.v ++++ b/mist/scandoubler.v +@@ -1,86 +1,164 @@ +-// simple scan doubler +- +-// c64 pixelclock = ~8Mhz +-// vga pixelclock = ~16Mhz ++// ++// scandoubler.v ++// ++// Copyright (c) 2015 Till Harbaum ++// ++// This source file is free software: you can redistribute it and/or modify ++// it under the terms of the GNU General Public License as published ++// by the Free Software Foundation, either version 3 of the License, or ++// (at your option) any later version. ++// ++// This source file is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++// ++// You should have received a copy of the GNU General Public License ++// along with this program. If not, see . ++ ++// TODO: Delay vsync one line + + module scandoubler ( +- // system interface +- input clk, // 32 MHz +- +- // c64 input +- input enable_in, // true on rising clock edge +- input [3:0] video_in, +- input vsync_in, +- input hsync_in, +- +- // vga output +- output [3:0] video_out, +- output vsync_out, +- output reg hsync_out ++ // system interface ++ input clk_x2, ++ ++ // scanlines (00-none 01-25% 10-50% 11-75%) ++ input [1:0] scanlines, ++ ++ // shifter video interface ++ input hs_in, ++ input vs_in, ++ input [5:0] r_in, ++ input [5:0] g_in, ++ input [5:0] b_in, ++ ++ // output interface ++ output reg hs_out, ++ output reg vs_out, ++ output reg [5:0] r_out, ++ output reg [5:0] g_out, ++ output reg [5:0] b_out + ); + +-localparam SYNC_WIDTH = 10'd16; ++reg clk; ++always @(posedge clk_x2) clk <= ~clk; ++ ++// --------------------- create output signals ----------------- ++// latch everything once more to make it glitch free and apply scanline effect ++reg scanline; ++always @(posedge clk_x2) begin ++ hs_out <= hs_sd; ++ vs_out <= vs_in; ++ ++ // reset scanlines at every new screen ++ if(vs_out != vs_in) ++ scanline <= 1'b0; ++ ++ // toggle scanlines at begin of every hsync ++ if(hs_out && !hs_sd) ++ scanline <= !scanline; ++ ++ // if no scanlines or not a scanline ++ if(!scanline || scanlines == 2'b00) begin ++ r_out <= sd_out[17:12]; ++ g_out <= sd_out[11:6]; ++ b_out <= sd_out[5:0]; ++ end else begin ++ case(scanlines) ++ 2'b01: begin // reduce 25% = 1/2 + 1/4 ++ r_out <= { 1'b0, sd_out[17:13] } + { 2'b00, sd_out[17:14] }; ++ g_out <= { 1'b0, sd_out[11:7] } + { 2'b00, sd_out[11:8] }; ++ b_out <= { 1'b0, sd_out[5:1] } + { 2'b00, sd_out[5:2] }; ++ end ++ ++ 2'b10: begin // reduce 50% = 1/2 ++ r_out <= { 1'b0, sd_out[17:13] }; ++ g_out <= { 1'b0, sd_out[11:7] }; ++ b_out <= { 1'b0, sd_out[5:1] }; ++ end ++ ++ 2'b11: begin // reduce 75% = 1/4 ++ r_out <= { 2'b00, sd_out[17:14] }; ++ g_out <= { 2'b00, sd_out[11:8] }; ++ b_out <= { 2'b00, sd_out[5:2] }; ++ end ++ endcase ++ end // else: !if(!scanline || scanlines == 2'b00) ++end ++ ++// scan doubler output register ++reg [17:0] sd_out; ++ ++// ================================================================== ++// ======================== the line buffers ======================== ++// ================================================================== ++ ++// 2 lines of 1024 pixels 3*6 bit RGB ++reg [17:0] sd_buffer [2047:0]; ++ ++// use alternating sd_buffers when storing/reading data ++reg vsD; ++reg line_toggle; ++always @(negedge clk) begin ++ vsD <= vs_in; + +-assign vsync_out = !vsync_in; ++ if(vsD != vs_in) ++ line_toggle <= 1'b0; + +-// sync is 64 pixel clocks wide and the whole screen is max 65*8=520. Thus a 10 bit +-// counter is sufficient ++ // begin of incoming hsync ++ if(hsD && !hs_in) ++ line_toggle <= !line_toggle; ++end ++ ++always @(negedge clk) ++ sd_buffer[{line_toggle, hcnt}] <= { r_in, g_in, b_in }; ++ ++// ================================================================== ++// =================== horizontal timing analysis =================== ++// ================================================================== ++ ++// total hsync time (in 16MHz cycles), hs_total reaches 1024 ++reg [9:0] hs_max; ++reg [9:0] hs_rise; + reg [9:0] hcnt; +-wire [9:0] pixel_addr = hcnt - SYNC_WIDTH; +-reg [9:0] hcnt_max; +-reg last_hsync_in; +- +-// The sync pulse width is 16 Pixels leaving a total of 520-16=504 max Pixels +-reg [3:0] buffer [1023:0]; +- +-// run output counter at twice the speed +-reg [9:0] vga_hcnt; +-wire [9:0] vga_pixel_addr = vga_hcnt - SYNC_WIDTH; +-reg vga_clk; +- +-reg line_toggle; ++reg hsD; ++ ++always @(negedge clk) begin ++ hsD <= hs_in; ++ ++ // falling edge of hsync indicates start of line ++ if(hsD && !hs_in) begin ++ hs_max <= hcnt; ++ hcnt <= 10'd0; ++ end else ++ hcnt <= hcnt + 10'd1; ++ ++ // save position of rising edge ++ if(!hsD && hs_in) ++ hs_rise <= hcnt; ++end ++ ++// ================================================================== ++// ==================== output timing generation ==================== ++// ================================================================== + +-assign video_out = (!hsync_out)?4'b0000:video_out_reg; ++reg [9:0] sd_hcnt; ++reg hs_sd; + +-reg [3:0] video_out_reg; ++// timing generation runs 32 MHz (twice the input signal analysis speed) ++always @(posedge clk_x2) begin + +-// analyze hsync signal +-always @(posedge clk) begin ++ // output counter synchronous to input and at twice the rate ++ sd_hcnt <= sd_hcnt + 10'd1; ++ if(hsD && !hs_in) sd_hcnt <= hs_max; ++ if(sd_hcnt == hs_max) sd_hcnt <= 10'd0; + +- // vga counter runs at twice the hcnt speed +- if(vga_clk) begin +- // read from line buffer +- video_out_reg <= buffer[{line_toggle, vga_pixel_addr[8:0]}]; +- +- if(vga_hcnt == hcnt_max) begin +- vga_hcnt <= 10'd0; +- hsync_out <= 1'b0; +- end else +- vga_hcnt <= vga_hcnt + 10'd1; +- +- if(vga_hcnt == SYNC_WIDTH) +- hsync_out <= 1'b1; +- end ++ // replicate horizontal sync at twice the speed ++ if(sd_hcnt == hs_max) hs_sd <= 1'b0; ++ if(sd_hcnt == hs_rise) hs_sd <= 1'b1; + +- if(enable_in) begin +- last_hsync_in <= hsync_in; +- vga_clk <= 1'b0; +- +- // write to line buffer +- if(hcnt >= SYNC_WIDTH) +- buffer[{!line_toggle, pixel_addr[8:0]}] <= video_in; +- +- // rising edge of hsync +- if(!last_hsync_in && hsync_in) begin +- line_toggle <= !line_toggle; +- vga_hcnt <= 10'd0; +- hcnt_max <= hcnt; +- hcnt <= 10'd0; +- end else +- hcnt <= hcnt + 10'd1; +- end else +- vga_clk <= !vga_clk; +- ++ // read data from line sd_buffer ++ sd_out <= sd_buffer[{~line_toggle, sd_hcnt}]; + end +- ++ + endmodule +diff --git a/rtl_dar/c64_mist.vhd b/rtl_dar/c64_mist.vhd +index 50254a0..74f7676 100644 +--- a/rtl_dar/c64_mist.vhd ++++ b/rtl_dar/c64_mist.vhd +@@ -201,12 +201,34 @@ component osd + -- VGA signals going to video connector + red_out : out std_logic_vector(5 downto 0); + green_out : out std_logic_vector(5 downto 0); +- blue_out : out std_logic_vector(5 downto 0); +- hs_out : out std_logic; +- vs_out : out std_logic ++ blue_out : out std_logic_vector(5 downto 0) + ); + end component osd; + ++--------- ++-- Scan doubler ++--------- ++component scandoubler is ++port ( ++ clk_x2 : in std_logic; ++ scanlines : in std_logic_vector(1 downto 0); ++ ++ -- c64 input ++ r_in : in std_logic_vector(5 downto 0); ++ g_in : in std_logic_vector(5 downto 0); ++ b_in : in std_logic_vector(5 downto 0); ++ hs_in : in std_logic; ++ vs_in : in std_logic; ++ ++ -- vga output ++ r_out : out std_logic_vector(5 downto 0); ++ g_out : out std_logic_vector(5 downto 0); ++ b_out : out std_logic_vector(5 downto 0); ++ hs_out : out std_logic; ++ vs_out : out std_logic ++); ++end component; ++ + ---------- + -- data_io + ---------- +@@ -278,7 +300,6 @@ end component sigma_delta_dac; + signal c64_g : std_logic_vector(5 downto 0); + signal c64_b : std_logic_vector(5 downto 0); + signal status : std_logic_vector(7 downto 0); +- signal scandoubler_disable: std_logic; + + signal sd_lba : std_logic_vector(31 downto 0); + signal sd_rd : std_logic; +@@ -343,6 +364,16 @@ end component sigma_delta_dac; + signal vsync : std_logic; + signal csync : std_logic; + ++ signal r_sd : std_logic_vector(5 downto 0); ++ signal g_sd : std_logic_vector(5 downto 0); ++ signal b_sd : std_logic_vector(5 downto 0); ++ signal hsync_out : std_logic; ++ signal vsync_out : std_logic; ++ signal hsync_osd : std_logic; ++ signal vsync_osd : std_logic; ++ signal hsync_sd : std_logic; ++ signal vsync_sd : std_logic; ++ + signal audio_data : std_logic_vector(17 downto 0); + + signal reset_counter : std_logic_vector(7 downto 0); +@@ -381,7 +412,7 @@ begin + status => status, + -- switches => switches, + buttons => buttons, +- scandoubler_disable => scandoubler_disable, ++ scandoubler_disable => tv15Khz_mode, + + sd_lba => sd_lba, + sd_rd => sd_rd, +@@ -501,7 +532,7 @@ begin + end process; + + -- route video through osd +- osdclk <= clk16 when tv15Khz_mode='0' else clk8; ++ osdclk <= clk32 when tv15Khz_mode='0' else clk16; + osd_d : osd + generic map (OSD_COLOR => 4) + port map ( +@@ -514,15 +545,16 @@ begin + red_in => c64_r, + green_in => c64_g, + blue_in => c64_b, +- hs_in => hsync, +- vs_in => vsync, ++ hs_in => hsync_osd, ++ vs_in => vsync_osd, + + red_out => VGA_R, + green_out => VGA_G, + blue_out => VGA_B + ); + +- tv15Khz_mode <= scandoubler_disable; ++ hsync_osd <= hsync_out when tv15Khz_mode='1' else hsync_sd; ++ vsync_osd <= vsync_out when tv15Khz_mode='1' else vsync_sd; + ntsc_init_mode <= status(2); + + pll_locked <= pll_locked_in(0) and pll_locked_in(1); +@@ -630,9 +662,7 @@ begin + ramDataIn => c64_data_in_int, + ramCE => ram_ce, + ramWe => ram_we, +- tv15Khz_mode => tv15Khz_mode, + ntscInitMode => ntsc_init_mode, +- scanlines => status(4), + hsync => hsync, + vsync => vsync, + r => r, +@@ -716,21 +746,41 @@ begin + led => led_disk + ); + +- c64_r <= std_logic_vector(r(7 downto 2)); +- c64_g <= std_logic_vector(g(7 downto 2)); +- c64_b <= std_logic_vector(b(7 downto 2)); ++ sd: scandoubler ++ port map( ++ clk_x2 => clk32, ++ scanlines => '0' & status(4), ++ ++ r_in => std_logic_vector(r(7 downto 2)), ++ g_in => std_logic_vector(g(7 downto 2)), ++ b_in => std_logic_vector(b(7 downto 2)), ++ hs_in => hsync_out, ++ vs_in => vsync_out, ++ ++ r_out => r_sd, ++ g_out => g_sd, ++ b_out => b_sd, ++ hs_out => hsync_sd, ++ vs_out => vsync_sd ++ ); ++ ++ c64_r <= std_logic_vector(r(7 downto 2)) when tv15Khz_mode = '1' else r_sd; ++ c64_g <= std_logic_vector(g(7 downto 2)) when tv15Khz_mode = '1' else g_sd; ++ c64_b <= std_logic_vector(b(7 downto 2)) when tv15Khz_mode = '1' else b_sd; + + comp_sync : entity work.composite_sync + port map( + clk32 => clk32, +- hsync => hsync, +- vsync => vsync, ++ hsync => not hsync, ++ vsync => not vsync, ++ hsync_out => hsync_out, ++ vsync_out => vsync_out, + csync => csync + ); + + -- synchro composite/ synchro horizontale +- VGA_HS <= csync when tv15Khz_mode = '1' else hsync; ++ VGA_HS <= csync when tv15Khz_mode = '1' else not hsync_sd; + -- commutation rapide / synchro verticale +- VGA_VS <= '1' when tv15Khz_mode = '1' else vsync; ++ VGA_VS <= '1' when tv15Khz_mode = '1' else not vsync_sd; + + end struct; +diff --git a/rtl_dar/composite_sync.vhd b/rtl_dar/composite_sync.vhd +index c18e34b..5860a52 100644 +--- a/rtl_dar/composite_sync.vhd ++++ b/rtl_dar/composite_sync.vhd +@@ -17,6 +17,8 @@ port( + hsync : in std_logic; + vsync : in std_logic; + csync : out std_logic; ++ hsync_out : out std_logic; ++ vsync_out : out std_logic; + blank : out std_logic + ); + end composite_sync ; +@@ -51,6 +53,7 @@ process(clk32) + end process; + + dot_clk <= clk_cnt(1); ++hsync_out <= not hsync0; + + process(dot_clk) + variable dot_count : integer range 0 to 1023 := 0; +@@ -102,6 +105,11 @@ process(dot_clk) + elsif line_count = 011 then csync <= hsync0; + else csync <= hsync0; + end if; ++ ++ if (line_count >= 001) and (line_count <= 010) ++ then vsync_out <= '1'; ++ else vsync_out <= '0'; ++ end if; + + -- PAL (seem not correct for NSTC) + -- +diff --git a/rtl_dar/fpga64_sid_iec.vhd b/rtl_dar/fpga64_sid_iec.vhd +index 879c1ab..4f8a85e 100644 +--- a/rtl_dar/fpga64_sid_iec.vhd ++++ b/rtl_dar/fpga64_sid_iec.vhd +@@ -54,9 +54,7 @@ entity fpga64_sid_iec is + idle: out std_logic; + + -- VGA/SCART interface +- tv15Khz_mode : in std_logic; + ntscInitMode : in std_logic; +- scanlines : in std_logic; + hsync: out std_logic; + vsync: out std_logic; + r : out unsigned(7 downto 0); +@@ -115,23 +113,6 @@ architecture rtl of fpga64_sid_iec is + CYCLE_CPUC, CYCLE_CPUD, CYCLE_CPUE, CYCLE_CPUF + ); + +- component scandoubler is +- port ( +- clk : in std_logic; -- 32 MHz +- +- -- c64 input +- enable_in : in std_logic; -- true on rising clock edge +- video_in : in std_logic_vector(3 downto 0); +- vsync_in : in std_logic; +- hsync_in : in std_logic; +- +- -- vga output +- video_out : out std_logic_vector(3 downto 0); +- vsync_out : out std_logic; +- hsync_out : out std_logic +- ); +- end component; +- + signal sysCycle : sysCycleDef := sysCycleDef'low; + signal sysCycleCnt : unsigned(2 downto 0); + signal phi0_cpu : std_logic; +@@ -235,8 +216,6 @@ architecture rtl of fpga64_sid_iec is + signal trace2Key : std_logic; + + -- video +- signal ColorIndex : unsigned(3 downto 0); +- + signal vicColorIndex : unsigned(3 downto 0); + signal vicHSync : std_logic; + signal vicVSync : std_logic; +@@ -369,62 +348,16 @@ begin + end if; + end process; + +--- ----------------------------------------------------------------------- +--- Scan-converter and VGA output +--- ----------------------------------------------------------------------- +- scandoubler_d: scandoubler +- port map +- ( +- clk => clk32, +- enable_in => enablePixel, +- video_in => std_logic_vector(vicColorIndex), +- hsync_in => vicHSync, +- vsync_in => vicVSync, +- video_out => vgaColorIndex_int, +- hsync_out => vgaHSync, +- vsync_out => vgaVSync +- ); +- +- ColorIndex <= vicColorIndex when tv15Khz_mode = '1' else vgaColorIndex; ++ hSync <= vicHSync; ++ vSync <= vicVSync; + + c64colors: entity work.fpga64_rgbcolor + port map ( +- index => ColorIndex, +- r => vgaR, +- g => vgaG, +- b => vgaB ++ index => vicColorIndex, ++ r => r, ++ g => g, ++ b => b + ); +- +- -- toggle odd/even vga lines +- process(vgaVSync, vgaHSync) +- begin +- if(vgaVSync = '0') then +- scanline <= '0'; +- else +- if rising_edge(vgaHSync) then +- scanline <= not scanline; +- end if; +- end if; +- end process; +- +- process(clk32) +- begin +- if rising_edge(clk32) then +- r <= vgaR; +- g <= vgaG; +- b <= vgaB; +- +- if((scanline = '1') and (tv15Khz_mode = '0') and (scanlines='1')) then +- r <= "0" & vgaR(7 downto 1); +- g <= "0" & vgaG(7 downto 1); +- b <= "0" & vgaB(7 downto 1); +- end if; +- end if; +- end process; +- +- hSync <= not vicHSync when tv15Khz_mode = '1' else vgaHSync; +- vSync <= not vicVSync when tv15Khz_mode = '1' else vgaVSync; +- + -- ----------------------------------------------------------------------- + -- Color RAM + -- ----------------------------------------------------------------------- +-- +1.8.3.msysgit.0 +