diff --git a/cores/archie/bench/rtl/a23_core.cpp b/cores/archie/bench/rtl/a23_core.cpp deleted file mode 100644 index 3e3c3da..0000000 --- a/cores/archie/bench/rtl/a23_core.cpp +++ /dev/null @@ -1,160 +0,0 @@ -#include // Defines common routines -#include "Va23_core.h" -#include "verilated_vcd_c.h" -#include -#include -#include -#include -#include -#include - -Va23_core *uut; // Instantiation of module -unsigned int *main_memory = NULL; -unsigned int *rom_memory = NULL; - -vluint64_t main_time = 0; // Current simulation time -// This is a 64-bit integer to reduce wrap over issues and -// allow modulus. You can also use a double, if you wish. -double sc_time_stamp () { // Called by $time in Verilog - return main_time; // converts to double, to match - // what SystemC does -} - -class Edge -{ -public: - Edge() - { - m_NegEdge = false; - m_PosEdge = false; - m_LastValue = false; - } - - void Update(bool value) - { - m_PosEdge = value & ~ m_LastValue; - m_NegEdge = ~value & m_LastValue; - m_LastValue = value; - } - - bool PosEdge() { return m_PosEdge; } - bool NegEdge() { return m_NegEdge; } - -private: - bool m_NegEdge; - bool m_PosEdge; - bool m_LastValue; -}; - -#define MEMTOP 8*1024*1024 - -int main(int argc, char** argv) { - - Edge vsync; - Edge hsync; - Edge cpuclk; - Edge pixclk; - - main_memory = (unsigned int *) malloc(MEMTOP); // 8MB of ram area. - - std::string fileName; - - if (argc > 1) - { - fileName = std::string(argv[1]); - } - - std::cout << fileName << std::endl; - - FILE *fp = fopen(fileName.c_str(), "r"); - if (fp == NULL) - { - std::cerr << "failed to open file: " << fileName << std::endl; - exit(-1); - } - - fseek(fp, 0L, SEEK_END); - size_t sz = ftell(fp); - fseek(fp, 0L, SEEK_SET); - - std::cerr << fread(main_memory, sizeof(char), sz, fp) << std::endl; - fclose(fp); - - Verilated::commandArgs(argc, argv); // Remember args - uut = new Va23_core; // Create instance - - Verilated::traceEverOn(true); - VerilatedVcdC* tfp = new VerilatedVcdC; - uut->trace(tfp, 99); - std::string vcdname = fileName + ".vcd"; - tfp->open(vcdname.c_str()); - - uut->i_irq = 0; - uut->i_firq = 0; - - while (!Verilated::gotFinish()) - { - if (main_time > 32) - { - uut->i_system_rdy = 1; // Deassert reset - } - - if ((main_time % 2) == 0) - { - uut->i_clk = uut->i_clk ? 0 : 1; // Toggle clock - } - - cpuclk.Update(uut->i_clk); - - uut->eval(); // Evaluate model - tfp->dump (main_time); - - if (uut->o_wb_stb && cpuclk.PosEdge() && !(bool)uut->i_wb_ack) - { - if (uut->o_wb_we) - { - unsigned int mask = 0; - if (uut->o_wb_sel & 1) mask |= 0xFF; - if (uut->o_wb_sel & 2) mask |= 0xFF00; - if (uut->o_wb_sel & 4) mask |= 0xFF0000; - if (uut->o_wb_sel & 8) mask |= 0xFF000000; - - if (uut->o_wb_adr < MEMTOP) - { - main_memory[uut->o_wb_adr >> 2] = uut->o_wb_dat & mask | main_memory[uut->o_wb_adr >> 2] & ~mask; - } - } - else - { - if (uut->o_wb_adr < MEMTOP) - { - uut->i_wb_dat = main_memory[uut->o_wb_adr >> 2]; - } - else - { - uut->i_wb_dat = 0; - } - } - - uut->i_wb_ack = 1; - - } - else if (cpuclk.PosEdge()) - { - uut->i_wb_ack = 0; - } - - main_time++; // Time passes... - - if (uut->o_wb_adr >= sz-4) - { - //std::cerr << main_time << std::endl; - //break; - } - } - - uut->final(); // Done simulating - tfp->close(); - delete uut; - -} diff --git a/cores/archie/bench/rtl/archimedes_bench_top.v b/cores/archie/bench/rtl/archimedes_bench_top.v deleted file mode 100644 index 7ab60df..0000000 --- a/cores/archie/bench/rtl/archimedes_bench_top.v +++ /dev/null @@ -1,326 +0,0 @@ -`timescale 1ns / 1ps -// archimedes_top_tb.v -// -// Archimedes top testbench -// -// Copyright (c) 2014 Stephen J. Leary -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -module archimedes_top_tb(); - - wire O_HSYNC; - wire O_VSYNC; - - wire [3:0] O_VIDEO_R; - wire [3:0] O_VIDEO_G; - wire [3:0] O_VIDEO_B; - - reg [32:0] clk_count2 = 0 ; - reg [64:0] clk_count = 0 ; - reg testfail = 0; - -// generated clocks -reg clk_32m /* synthesis keep */ ; -reg clk_128m /* synthesis keep */ ; -reg clk_24m /* synthesis keep */ ; -reg clk_25m /* synthesis keep */ ; -reg clk_36m /* synthesis keep */ ; - -// data loading -wire loader_active /* synthesis keep */ ; -wire loader_we /* synthesis keep */ ; -reg loader_stb = 1'b0 /* synthesis keep */ ; -(*KEEP="TRUE"*)wire [3:0] loader_sel /* synthesis keep */ ; -(*KEEP="TRUE"*)wire [23:0] loader_addr /* synthesis keep */ ; -(*KEEP="TRUE"*)wire [31:0] loader_data /* synthesis keep */ ; - -// the top file should generate the correct clocks for the machine - -fakedata_io data_io ( - .rst ( ~ram_ready ), - .sck ( SPI_SCK ), - .ss ( SPI_SS2 ), - .sdi ( SPI_DI ), - - .downloading ( loader_active ), - .size ( ), - - // ram interface - .clk ( clk_32m ), - .wr ( loader_we ), - .a ( loader_addr ), - .sel ( loader_sel ), - .d ( loader_data ) -); - - - // SDRAM - wire [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits - wire [12:0] DRAM_A; // SDRAM Address bus 13 Bits - wire [1:0] DRAM_DQM; // SDRAM Low-byte Data Mask - wire DRAM_WE_N; // SDRAM Write Enable - wire DRAM_CAS_N; // SDRAM Column Address Strobe - wire DRAM_RAS_N; // SDRAM Row Address Strobe - wire DRAM_CS_N; // SDRAM Chip Select - wire [1:0] DRAM_BA; // SDRAM Bank Address - wire DRAM_CLK; // SDRAM Clock - wire DRAM_CKE; // SDRAM Clock Enable - - -mt48lc16m16a2 RAM( - - .Dq (DRAM_DQ), - .Addr (DRAM_A ), - .Ba (DRAM_BA), - .Clk (DRAM_CLK), - .Cke (DRAM_CKE), - .Cs_n (DRAM_CS_N), - .Ras_n (DRAM_RAS_N), - .Cas_n (DRAM_CAS_N), - .We_n (DRAM_WE_N), - .Dqm (DRAM_DQM) -); - - -wire clk_pix; -wire clk_pix2x; - -reg pll_ready = 0; - -reg core_reset = 0; - -reg [64:0] CLOCK_CYCLES = 64'd0 /* synthesis preserve */; -wire ram_ready; - -// core's raw video -wire [3:0] core_r, core_g, core_b; -wire core_hs, core_vs; - - -// the top file should generate the correct clocks for the machine - -wire core_ack_in /* synthesis keep */ ; -wire core_stb_out /* synthesis keep */ ; -wire core_cyc_out /* synthesis keep */ ; -wire core_we_o; -wire [2:0] core_cti_o; -wire [3:0] core_sel_o; -wire [31:0] core_data_in, core_data_out; -wire [31:0] ram_data_in; -wire [26:2] core_address_out; - -wire [1:0] pixbaseclk_select; - -wire i2c_din, i2c_dout, i2c_clock; - -archimedes_top ARCHIMEDES( - - .CLKCPU_I ( clk_32m ), - .CLKPIX2X_I ( clk_pix2x ), // pixel clock x 2 - .CLKPIX_O ( clk_pix ), // pixel clock for OSD - - .RESET_I (~ram_ready | loader_active), - - .MEM_ACK_I ( core_ack_in ), - .MEM_DAT_I ( core_data_in ), - .MEM_DAT_O ( core_data_out ), - .MEM_ADDR_O ( core_address_out), - .MEM_STB_O ( core_stb_out ), - .MEM_CYC_O ( core_cyc_out ), - .MEM_SEL_O ( core_sel_o ), - .MEM_WE_O ( core_we_o ), - .MEM_CTI_O ( core_cti_o ), - - .HSYNC ( core_hs ), - .VSYNC ( core_vs ), - .VIDEO_R ( core_r ), - .VIDEO_G ( core_g ), - .VIDEO_B ( core_b ), - - .I2C_DOUT ( i2c_din ), - .I2C_DIN ( i2c_dout ), - .I2C_CLOCK ( i2c_clock ), - - .DEBUG_LED ( LED ), - - .KBD_OUT_DATA ( kbd_out_data ), - .KBD_OUT_STROBE ( kbd_out_strobe ), - .KBD_IN_DATA ( kbd_in_data ), - .KBD_IN_STROBE ( kbd_in_strobe ), - - .JOYSTICK0 ( joyA[4:0] ), - .JOYSTICK1 ( joyB[4:0] ), - .VIDBASECLK_O ( pixbaseclk_select ), - .VIDSYNCPOL_O ( ) -); - -wire ram_ack /* synthesis keep */ ; -wire ram_stb /* synthesis keep */ ; -wire ram_cyc /* synthesis keep */ ; -wire ram_we /* synthesis keep */ ; -wire [3:0] ram_sel /* synthesis keep */ ; -wire [2:0] ram_cti /* synthesis keep */ ; -wire [25:0] ram_address/* synthesis keep */ ; - -sdram_top SDRAM( - - // wishbone interface - .wb_clk ( clk_32m ), - .wb_stb ( ram_stb ), - .wb_cyc ( ram_cyc ), - .wb_we ( ram_we ), - .wb_ack ( ram_ack ), - - .wb_sel ( ram_sel ), - .wb_adr ( ram_address ), - .wb_dat_i ( ram_data_in ), - .wb_dat_o ( core_data_in ), - .wb_cti ( ram_cti ), - - // SDRAM Interface - .sd_clk ( clk_128m ), - .sd_rst ( ~pll_ready ), - .sd_cke ( DRAM_CKE ), - - .sd_dq ( DRAM_DQ ), - .sd_addr ( DRAM_A ), - .sd_dqm ( DRAM_DQM ), - .sd_cs_n ( DRAM_CS_N ), - .sd_ba ( DRAM_BA ), - .sd_we_n ( DRAM_WE_N ), - .sd_ras_n ( DRAM_RAS_N ), - .sd_cas_n ( DRAM_CAS_N ), - .sd_ready ( ram_ready ) -); - - -i2cSlaveTop CMOS ( - .clk ( clk_32m ), - .rst ( ~pll_ready ), - .sdaIn ( i2c_din ), - .sdaOut ( i2c_dout ), - .scl ( i2c_clock ) -); - - -always @(posedge clk_32m) begin - - if (loader_we) begin - - loader_stb <= 1'b1; - - end else if (ram_ack) begin - - loader_stb <= 1'b0; - - end - -end - -assign ram_cti = loader_active ? 3'b000 : core_cti_o; -assign ram_we = loader_active ? loader_active : core_we_o; -assign ram_sel = loader_active ? loader_sel : core_sel_o; -assign ram_address = loader_active ? {loader_addr[23:2],2'b00} : {core_address_out[23:2],2'b00}; -assign ram_stb = loader_active ? loader_stb : core_stb_out; -assign ram_cyc = loader_active ? loader_stb : core_stb_out; -assign ram_data_in = loader_active ? loader_data : core_data_out; -assign core_ack_in = loader_active ? 1'b0 : ram_ack; - -assign DRAM_CLK = clk_128m; - -assign clk_pix2x = pixbaseclk_select == 2'b00 ? clk_24m : - pixbaseclk_select == 2'b01 ? clk_25m : - pixbaseclk_select == 2'b10 ? clk_36m : clk_24m; - - - -assign O_HSYNC = core_hs; -assign O_VSYNC = core_vs; - -assign O_VIDEO_R = core_r; -assign O_VIDEO_G = core_g; -assign O_VIDEO_B = core_b; - -task VSync; -begin -wait(~O_VSYNC); -$display("VSYNC: %g", $time); -wait(O_VSYNC); -end -endtask - - -initial begin - - $dumpfile("archimedes_top.vcd"); - $dumpvars(0, archimedes_top_tb); - $monitor ("%b %b %b %b", pll_ready, i2c_clock, i2c_din, i2c_dout); - //$readmemh("sram.vmem", ram); - // Initialize Inputs - clk_32m = 0; - clk_24m = 0; - clk_128m = 0; - clk_36m = 0; - clk_25m = 0; - - pll_ready = 0; - - #7764; - pll_ready = 1; - #500000; - - $writememh("bank0.hex", RAM.Bank0); - - - $finish; -end - -always -begin - #16; clk_32m = ~clk_32m; -end - -always -begin - #10; clk_24m = ~clk_24m; -end - -always -begin - #9; clk_25m = ~clk_25m; -end - -always begin - #7; clk_36m = ~clk_36m; -end - -always begin - #4; clk_128m = ~clk_128m; -end - -always @(posedge clk_32m) begin - CLOCK_CYCLES <= CLOCK_CYCLES + 63'd1; - clk_count <= clk_count + 63'd1; - clk_count2 <= clk_count2 + 1; - - if (clk_count2 >= 32'd0009999) begin - - $display("CLOCK_CYCLES: %d", clk_count); - clk_count2 <= 64'd0; - end - -end - -endmodule // archimedes_bench_top diff --git a/cores/archie/bench/rtl/archimedes_tb.v b/cores/archie/bench/rtl/archimedes_tb.v deleted file mode 100644 index f8c1a2c..0000000 --- a/cores/archie/bench/rtl/archimedes_tb.v +++ /dev/null @@ -1,237 +0,0 @@ -`timescale 1ns / 1ps -// archimedes_top_tb.v -// -// Archimedes top testbench -// -// Copyright (c) 2014 Stephen J. Leary -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -module archimedes_top_tb(); - - wire O_HSYNC; - wire O_VSYNC; - - wire [3:0] O_VIDEO_R; - wire [3:0] O_VIDEO_G; - wire [3:0] O_VIDEO_B; - - // SDRAM - wire [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits - wire [12:0] DRAM_ADDR; // SDRAM Address bus 13 Bits - wire [1:0] DRAM_DQM; // SDRAM Low-byte Data Mask - wire DRAM_WE_N; // SDRAM Write Enable - wire DRAM_CAS_N; // SDRAM Column Address Strobe - wire DRAM_RAS_N; // SDRAM Row Address Strobe - wire DRAM_CS_N; // SDRAM Chip Select - wire [1:0] DRAM_BA; // SDRAM Bank Address - wire DRAM_CLK; // SDRAM Clock - wire DRAM_CKE; // SDRAM Clock Enable - -// generated clocks -reg clk_32m /* synthesis keep */ ; -reg clk_128m /* synthesis keep */ ; -reg clk_24m /* synthesis keep */ ; -//wire clk_8m /* synthesis keep */ ; - -reg pll_ready; -wire ram_ready; - -// core's raw video -wire [3:0] core_r, core_g, core_b; -wire core_hs, core_vs; - -// data loading -wire loader_active /* synthesis keep */ ; -wire loader_we /* synthesis keep */ ; -reg loader_stb = 1'b0 /* synthesis keep */ ; -(*KEEP="TRUE"*)wire [3:0] loader_sel /* synthesis keep */ ; -(*KEEP="TRUE"*)wire [23:0] loader_addr /* synthesis keep */ ; -(*KEEP="TRUE"*)wire [31:0] loader_data /* synthesis keep */ ; - -// the top file should generate the correct clocks for the machine - -fakedata_io data_io ( - .rst ( ~ram_ready ), - .sck ( SPI_SCK ), - .ss ( SPI_SS2 ), - .sdi ( SPI_DI ), - - .downloading ( loader_active ), - .size ( ), - - // ram interface - .clk ( clk_32m ), - .wr ( loader_we ), - .a ( loader_addr ), - .sel ( loader_sel ), - .d ( loader_data ) -); - -mt48lc16m16a2 RAM( - - .Dq (DRAM_DQ), - .Addr (DRAM_ADDR), - .Ba (DRAM_BA), - .Clk (DRAM_CLK), - .Cke (DRAM_CKE), - .Cs_n (DRAM_CS_N), - .Ras_n (DRAM_RAS_N), - .Cas_n (DRAM_CAS_N), - .We_n (DRAM_WE_N), - .Dqm (DRAM_DQM) -); - -wire core_ack_in /* synthesis keep */ ; -wire core_stb_out /* synthesis keep */ ; -wire core_cyc_out /* synthesis keep */ ; -wire core_we_o; -wire [3:0] core_sel_o; -wire [31:0] core_data_in, core_data_out; -wire [26:2] core_address_out; - -archimedes_top ARCHIMEDES( - - .CLKCPU_I(clk_32m), - .CLKPIX_I(clk_24m), - .RESET_I(~ram_ready | loader_active), - - .MEM_ACK_I ( core_ack_in ), - .MEM_DAT_I ( core_data_in ), - .MEM_DAT_O ( core_data_out ), - .MEM_ADDR_O ( core_address_out), - .MEM_STB_O ( core_stb_out ), - .MEM_CYC_O ( core_cyc_out ), - .MEM_SEL_O ( core_sel_o ), - .MEM_WE_O ( core_we_o ), - - .HSYNC(core_hs), - .VSYNC(core_vs), - .VIDEO_R(core_r), - .VIDEO_G(core_g), - .VIDEO_B(core_b) -); - -wire ram_ack /* synthesis keep */ ; -wire ram_stb /* synthesis keep */ ; -wire ram_cyc /* synthesis keep */ ; -wire ram_we /* synthesis keep */ ; -wire [3:0] ram_sel /* synthesis keep */ ; -wire [25:0] ram_address/* synthesis keep */ ; - -sdram_top SDRAM( - - // wishbone interface - .wb_clk ( clk_32m ), - .wb_stb ( ram_stb ), - .wb_cyc ( ram_cyc ), - .wb_we ( ram_we ), - .wb_ack ( ram_ack ), - - .wb_sel ( ram_sel ), - .wb_adr ( ram_address ), - .wb_dat_i ( loader_data ), - .wb_dat_o ( core_data_in ), - .wb_cti ( 3'b000 ), - - // SDRAM Interface - .sd_clk ( clk_128m ), - .sd_rst ( ~pll_ready ), - .sd_cke ( DRAM_CKE ), - - .sd_dq ( DRAM_DQ ), - .sd_addr ( DRAM_A ), - .sd_dqm ( DRAM_DQM ), - .sd_cs_n ( DRAM_CS_N ), - .sd_ba ( DRAM_BA ), - .sd_we_n ( DRAM_WE_N ), - .sd_ras_n ( DRAM_RAS_N ), - .sd_cas_n ( DRAM_CAS_N ), - .sd_ready ( ram_ready ) - - ); - - -always @(posedge clk_32m) begin - - if (loader_we) begin - - loader_stb <= 1'b1; - - end else if (ram_ack) begin - - loader_stb <= 1'b0; - - end - -end - -assign ram_we = loader_active ? loader_active : core_we_o; -assign ram_sel = loader_active ? loader_sel : core_sel_o; -assign ram_address = loader_active ? {loader_addr[23:2],2'b00} : {core_address_out[23:2],2'b00}; -assign ram_stb = loader_active ? loader_stb : core_stb_out; -assign ram_cyc = loader_active ? loader_stb : core_stb_out; -assign core_ack_in = loader_active ? 1'b0 : ram_ack; - -assign DRAM_CLK = clk_128m; - -initial begin - - $dumpfile("archimedes_top.vcd"); - $dumpvars(0, archimedes_top_tb); - - // Initialize Inputs - clk_32m = 0; - clk_24m = 0; - clk_128m = 0; - - pll_ready = 0; - - #50; - pll_ready = 1; - - wait(loader_active); - wait(~loader_active); - - wait(~ARCHIMEDES.vid_flybk); - - wait(~O_HSYNC); - wait(O_HSYNC); - - wait(~O_HSYNC); - wait(O_HSYNC); - - wait(~O_HSYNC); - wait(O_HSYNC); - - // $writememh("bank0.hex", RAM.Bank0); - $finish; -end - -always -begin - #4; clk_128m = ~clk_128m; -end - -always -begin - #20; clk_24m = ~clk_24m; -end - -always -begin - #15; clk_32m = ~clk_32m; -end - -endmodule // archimedes_papoliopro_top diff --git a/cores/archie/bench/rtl/archimedes_top.cpp b/cores/archie/bench/rtl/archimedes_top.cpp deleted file mode 100644 index 8ee2264..0000000 --- a/cores/archie/bench/rtl/archimedes_top.cpp +++ /dev/null @@ -1,256 +0,0 @@ - -#include // Defines common routines -#include "Varchimedes_top.h" -#include "../i2cSlaveTop/Vi2cSlaveTop.h" -#include "verilated_vcd_c.h" -#include -#include -#include -#include // std::queue -#include -#include -#include -#include - -Varchimedes_top *uut; // Instantiation of module -Vi2cSlaveTop *i2c; -unsigned int *main_memory = NULL; -unsigned int *rom_memory = NULL; - -vluint64_t main_time = 0; // Current simulation time -// This is a 64-bit integer to reduce wrap over issues and -// allow modulus. You can also use a double, if you wish. -double sc_time_stamp () { // Called by $time in Verilog - return main_time; // converts to double, to match - // what SystemC does -} - -class Edge -{ -public: - Edge() - { - m_NegEdge = false; - m_PosEdge = false; - m_LastValue = false; - } - - void Update(bool value) - { - m_PosEdge = value & ~ m_LastValue; - m_NegEdge = ~value & m_LastValue; - m_LastValue = value; - } - - bool PosEdge() - { - return m_PosEdge; - } - bool NegEdge() - { - return m_NegEdge; - } - -private: - bool m_NegEdge; - bool m_PosEdge; - bool m_LastValue; -}; - -int main(int argc, char** argv) { - - //The images - SDL_Surface* screen = NULL; - SDL_Init(SDL_INIT_VIDEO); - //Set up screen - screen = SDL_SetVideoMode( 800, 524, 32, SDL_SWSURFACE | SDL_RESIZABLE ); - - //Update Screen - SDL_Flip( screen ); - - // Check that the window was successfully made - if (screen == NULL) - { - // In the event that the window could not be made... - printf("Could not create window: %s\n", SDL_GetError()); - return 1; - } - - // simulate a monitor - int xcount = 0; - int ycount = 0; - int frame = 0; - - Edge vsync; - Edge hsync; - Edge cpuclk; - Edge pixclk; - - main_memory = (unsigned int *) malloc(8*1024*1024); // 8MB of ram area. - rom_memory = main_memory + 1024*1024; - - std::string fileName = "ROM310"; - - FILE *fp = fopen(fileName.c_str(), "r"); - if (fp == NULL) - { - std::cerr << "failed to open file:" << fileName << std::endl; - exit(-1); - } - - fseek(fp, 0L, SEEK_END); - size_t sz = ftell(fp); - fseek(fp, 0L, SEEK_SET); - - std::cerr << fread(rom_memory, sizeof(char), sz, fp) << std::endl; - fclose(fp); - - Verilated::commandArgs(argc, argv); // Remember args - uut = new Varchimedes_top; // Create instance - i2c = new Vi2cSlaveTop; // Create I2C instance - - Verilated::traceEverOn(true); - VerilatedVcdC* tfp = new VerilatedVcdC; - uut->trace(tfp, 99); - tfp->open("archimedes_top.vcd"); - - uut->RESET_I = 1; - - Uint8 *p = (Uint8 *)screen->pixels; - - bool burst = false; - uint32_t burst_address = 0; - - while (!Verilated::gotFinish()) - { - if (main_time > 32) - { - uut->RESET_I = 0; // Deassert reset - } - - if ((main_time % 2) == 0) - { - uut->CLKCPU_I = uut->CLKCPU_I ? 0 : 1; // Toggle clock - } - - if ((main_time % 3) == 0) - { - uut->CLKPIX2X_I = uut->CLKPIX2X_I ? 0 : 1; // Toggle clock - } - - cpuclk.Update(uut->CLKCPU_I); - pixclk.Update(uut->CLKPIX_O); - vsync.Update(uut->VSYNC); - hsync.Update(uut->HSYNC); - - i2c->clk = uut->CLKCPU_I; - i2c->rst = uut->RESET_I; - i2c->sdaIn = uut->I2C_DOUT; - uut->I2C_DIN = i2c->sdaOut; - i2c->scl = uut->I2C_CLOCK; - - uut->eval(); // Evaluate model - i2c->eval(); - - // this code dumps a time section - // needs a clock counter in archimedes_top.v (missing) - /*if ((uut->v__DOT__clk_count > 8137000) && (uut->v__DOT__clk_count < 8138000)) - { - tfp->dump (main_time); - }*/ - - if (uut->MEM_STB_O && cpuclk.PosEdge() && !(bool)uut->MEM_ACK_I) - { - if (uut->MEM_WE_O) - { - unsigned int mask = 0; - if (uut->MEM_SEL_O & 1) mask |= 0xFF; - if (uut->MEM_SEL_O & 2) mask |= 0xFF00; - if (uut->MEM_SEL_O & 4) mask |= 0xFF0000; - if (uut->MEM_SEL_O & 8) mask |= 0xFF000000; - - if ((uut->MEM_ADDR_O << 2) >= 4*1024*1024) - { - std::cerr << "Managed to write to ROM" << std::endl; - break; - } - - main_memory[uut->MEM_ADDR_O] = uut->MEM_DAT_O & mask | main_memory[uut->MEM_ADDR_O] & ~mask; - } - else if (uut->MEM_CTI_O == 2) - { - uut->MEM_DAT_I = main_memory[uut->MEM_ADDR_O]; - burst = true; - burst_address = uut->MEM_ADDR_O; - } - else - { - uut->MEM_DAT_I = main_memory[uut->MEM_ADDR_O]; - } - - uut->MEM_ACK_I = 1; - } - - else if (cpuclk.PosEdge()) - { - if (uut->MEM_CYC_O && (uut->MEM_CTI_O == 2)) - { - uut->MEM_DAT_I = main_memory[++burst_address]; - burst = false; - } - else - { - uut->MEM_ACK_I = 0; - } - } - - if (vsync.PosEdge()) - { - SDL_Flip( screen ); - p = (Uint8 *)screen->pixels; - - std::cerr << "frame: " << frame << " " << ycount << std::endl; - ycount = 0; - xcount = 0; - frame++; - } - else if (hsync.PosEdge()) - { - //std::cerr << xcount << std::endl; - ycount++; - xcount = 0; - // std::cerr << (uut->VSYNC ? true : false) << " sync: xcount " << xcount << " ycount " << ycount << std::endl; - //SDL_Flip( screen ); - p = (Uint8 *)screen->pixels; - p+= ycount * screen->w *4; - } - - else if (pixclk.PosEdge() && (bool)uut->VSYNC && (bool) uut->HSYNC) - { - if ((ycount < screen->h) && (xcount <= screen->w)) - { - - - *p++ = ((unsigned char)uut->VIDEO_B) << 4 | (unsigned char)uut->VIDEO_B; - *p++ = ((unsigned char)uut->VIDEO_G) << 4 | (unsigned char)uut->VIDEO_G; - *p++ = ((unsigned char)uut->VIDEO_R) << 4 | (unsigned char)uut->VIDEO_R; - p++; - //((((unsigned char)uut->VIDEO_G) & 0xc) << 1) | ((((unsigned char)uut->VIDEO_B) & 0xe) >> 1); - xcount++; - } - } - - - - main_time++; // Time passes... -} - - tfp->close(); - uut->final(); // Done simulating - // // (Though this example doesn't get here) - - //Quit SDL - SDL_Quit(); - - delete uut; -} diff --git a/cores/archie/bench/rtl/archimedes_top_instrumented.cpp b/cores/archie/bench/rtl/archimedes_top_instrumented.cpp deleted file mode 100644 index a2ed5a2..0000000 --- a/cores/archie/bench/rtl/archimedes_top_instrumented.cpp +++ /dev/null @@ -1,405 +0,0 @@ -#include // Defines common routines -#include "Varchimedes_top_instrumented.h" -#include "verilated_vcd_c.h" -#include -#include -#include -#include // std::queue -#include -#include -#include -#include - -Varchimedes_top_instrumented *uut; // Instantiation of module -unsigned int *main_memory = NULL; -unsigned int *rom_memory = NULL; - -struct cpuaccess -{ - signed char we; - unsigned int address; - unsigned int dat; - unsigned int be; // byte enable; - unsigned int expected; - unsigned int time; -}; - - signed long long delta = 0; - vluint64_t num_cycles = 0; - -vluint64_t main_time = 0; // Current simulation time -// This is a 64-bit integer to reduce wrap over issues and -// allow modulus. You can also use a double, if you wish. -double sc_time_stamp () { // Called by $time in Verilog - return main_time; // converts to double, to match - // what SystemC does -} - -class Edge -{ -public: - Edge() - { - m_NegEdge = false; - m_PosEdge = false; - m_LastValue = false; - } - - void Update(bool value) - { - m_PosEdge = value & ~ m_LastValue; - m_NegEdge = ~value & m_LastValue; - m_LastValue = value; - } - - bool PosEdge() { return m_PosEdge; } - bool NegEdge() { return m_NegEdge; } - -private: - bool m_NegEdge; - bool m_PosEdge; - bool m_LastValue; -}; - -static std::string nextline; -unsigned int linecount = 0; - -bool LoadNextLine(std::istream& instream) -{ - linecount++; - return std::getline(instream,nextline); -} - -bool GetNextAccess(struct cpuaccess* access, std::istream& instream) -{ - bool result = false; - - std::string line = nextline; - - if (LoadNextLine(instream)) - { - std::cout << uut->v__DOT__clk_count << " | " << line << std::endl; - int x = sscanf(line.c_str(), "%i, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x", &(access->we), &(access->address), &(access->dat), &(access->be), &(access->expected), &(access->time)); - result = true; - } - - if (access->we == 2) - { - access->dat -= delta; - } - - - - - return result; -} - -int main(int argc, char** argv) { - - int i = 0; - - - cpuaccess* access = new cpuaccess; - - std::queue interrupt_queue; - cpuaccess* interrupt_nxt = NULL; - - - //The images - SDL_Surface* screen = NULL; - SDL_Init(SDL_INIT_VIDEO); - //Set up screen - screen = SDL_SetVideoMode( 800, 524, 32, SDL_SWSURFACE | SDL_RESIZABLE ); - - //Update Screen - SDL_Flip( screen ); - - // Check that the window was successfully made - if (screen == NULL) { - // In the event that the window could not be made... - printf("Could not create window: %s\n", SDL_GetError()); - return 1; - } - - // simulate a monitor - int xcount = 0; - int ycount = 0; - - Edge vsync; - Edge hsync; - Edge cpuclk; - Edge pixclk; - - main_memory = (unsigned int *) malloc(8*1024*1024); // 8MB of ram area. - rom_memory = main_memory + 1024*1024; - - std::string fileName = "../ROM310"; - if (argc > 1) - { - fileName = argv[1]; - } - - FILE *fp = fopen(fileName.c_str(), "r"); - if (fp == NULL) - { - std::cerr << "failed to open file" << std::endl; - exit(-1); - } - - std::cerr << fread(rom_memory, sizeof(char), 2*1024*1024, fp) << std::endl; - fclose(fp); - - Verilated::commandArgs(argc, argv); // Remember args - uut = new Varchimedes_top_instrumented; // Create instance - - LoadNextLine(std::cin); - GetNextAccess(access, std::cin); - - - Verilated::traceEverOn(true); - VerilatedVcdC* tfp = new VerilatedVcdC; - uut->trace(tfp, 99); - tfp->open("archimedes_top_instrumented.vcd"); - - uut->RESET_I = 1; // Set some inputs - uut->cpu_irq = 0; - uut->cpu_firq = 0; - uut->use_instrumented = 1; - - - Uint8 *p = (Uint8 *)screen->pixels; - - int mem_wait_states = 0; - - unsigned int lock_timer = 0; - bool locked = false; - int ttl = -1; - - while (!Verilated::gotFinish()) - { - locked = lock_timer > 0; - - if (main_time > 32) - { - uut->RESET_I = 0; // Deassert reset - } - - if ((main_time % 2) == 0) - { - uut->CLKCPU_I = uut->CLKCPU_I ? 0 : 1; // Toggle clock - } - - if ((main_time % 3) == 0) - { - uut->CLKPIX_I = uut->CLKPIX_I ? 0 : 1; // Toggle clock - } - - cpuclk.Update(uut->CLKCPU_I); - pixclk.Update(uut->CLKPIX_I); - vsync.Update(uut->VSYNC); - hsync.Update(uut->HSYNC); - - uut->eval(); // Evaluate model - - if ((uut->v__DOT__clk_count >= 48393910) && (uut->v__DOT__clk_count <= 48394006)) - { - tfp->dump (main_time); - } - - - if (uut->v__DOT__ARM__DOT__u_decode__DOT__u_decompile__DOT__inst_count == 8576761) - { - delta = 0; - } - - if (uut->MEM_STB_O && cpuclk.PosEdge() && !(bool)uut->MEM_ACK_I) - { - mem_wait_states++; - if (mem_wait_states > 1) - { - - //std::cout << "MEM: " << std::hex << (uut->MEM_ADDR_O << 2) << std::endl; - - if (uut->MEM_WE_O) - { - unsigned int mask = 0; - if (uut->MEM_SEL_O & 1) mask |= 0xFF; - if (uut->MEM_SEL_O & 2) mask |= 0xFF00; - if (uut->MEM_SEL_O & 4) mask |= 0xFF0000; - if (uut->MEM_SEL_O & 8) mask |= 0xFF000000; - - if ((uut->MEM_ADDR_O << 2) >= 4*1024*1024) - { - std::cerr << "Managed to write to ROM" << std::endl; - break; - } - - main_memory[uut->MEM_ADDR_O] = uut->MEM_DAT_O & mask | main_memory[uut->MEM_ADDR_O] & ~mask; - } - else - { - if ((uut->iospace) && !uut->v__DOT__cpu_we && uut->v__DOT__MEMC__DOT__cpu_load) - { - delta = uut->v__DOT__ARM__DOT__u_decode__DOT__u_decompile__DOT__inst_count; - delta -= (signed long long)access->time; - std::cout << "delta: " << (delta) << std::endl; - - if (abs(delta) > 20) - { - std::cerr << "Delta exceeded limits" << std::endl; - break; - } - - // read the memory access shit. - if ((unsigned int)(uut->v__DOT__cpu_address & 0x3fffffc) != (unsigned int)access->address) - { - std::cerr << uut->v__DOT__ARM__DOT__u_decode__DOT__u_decompile__DOT__inst_count << std::hex << " ERROR: expected address: " << (unsigned int)access->address << " accessed " << (unsigned int)uut->v__DOT__cpu_address << std::dec << " line " << linecount << std::endl; - ttl=2; // live for 10 more instructions - } - else - { - std::cout << uut->v__DOT__ARM__DOT__u_decode__DOT__u_decompile__DOT__inst_count << std::hex << " PASS: expected address: " << (unsigned int)access->address << " result " << access->expected << std::dec << std::endl; - } - - uut->MEM_DAT_I = access->expected; - - GetNextAccess(access, std::cin); - - // interrupt handling. - - while (access->we > 1) - { - cpuaccess *accesscopy = new cpuaccess; - memcpy(accesscopy, access, sizeof(cpuaccess)); - interrupt_queue.push(accesscopy); - - - - GetNextAccess(access, std::cin); - } - - } - else - { - uut->MEM_DAT_I = main_memory[uut->MEM_ADDR_O]; - } - - } - - if (uut->v__DOT__MEMC__DOT__cpu_load) - { - num_cycles++; - - if (ttl == 0) - { - break; - } - - if (ttl > 0) - { - ttl--; - } - - } - - mem_wait_states = 0; - uut->MEM_ACK_I = 1; - } - else - { - uut->MEM_ACK_I = 0; - } - - } - else if (cpuclk.PosEdge()) - { - uut->MEM_ACK_I = 0; - } - - // interrupt handling - - if (cpuclk.PosEdge() && (interrupt_nxt == NULL)) - { - if (!interrupt_queue.empty()) - { - interrupt_nxt = interrupt_queue.front(); - interrupt_queue.pop(); - } - } - - if (interrupt_nxt != NULL) - { - if ((uut->v__DOT__ARM__DOT__u_decode__DOT__u_decompile__DOT__inst_count) >= (interrupt_nxt->dat)) - { - if (interrupt_nxt->we == 2) - { - uut->cpu_irq = interrupt_nxt->expected ? 1 : 0; - std::cerr << uut->v__DOT__ARM__DOT__u_decode__DOT__u_decompile__DOT__inst_count << " irq state: " << (uut->cpu_irq ? 1 : 0) << " (" << interrupt_nxt->dat << ")" << std::endl; - } - - if (interrupt_nxt->we == 3) - { - uut->cpu_firq = interrupt_nxt->expected ? 1 : 0; - std::cerr << uut->v__DOT__ARM__DOT__u_decode__DOT__u_decompile__DOT__inst_count << " firq state: " << (uut->cpu_firq ? 1 : 0) << " (" << interrupt_nxt->dat << ")" << std::endl; - } - - delete interrupt_nxt; - interrupt_nxt = NULL; - } - else - { - - //std::cerr << uut->v__DOT__ARM__DOT__u_decode__DOT__u_decompile__DOT__inst_count << " (f)irq wait state: " << "(" << interrupt_nxt->dat << ")" << std::endl; - } - } - - - if (vsync.PosEdge()) - { - SDL_Flip( screen ); - p = (Uint8 *)screen->pixels; - - std::cerr << ycount << std::endl; - ycount = 0; - xcount = 0; - - } - else if (hsync.PosEdge()) - { - //std::cerr << xcount << std::endl; - ycount++; - xcount = 0; - // std::cerr << (uut->VSYNC ? true : false) << " sync: xcount " << xcount << " ycount " << ycount << std::endl; - //SDL_Flip( screen ); - p = (Uint8 *)screen->pixels; - p+= ycount * screen->w *4; - } - - else if (pixclk.PosEdge() && (bool)uut->VSYNC && (bool) uut->HSYNC) - { - if ((ycount < screen->h) && (xcount <= screen->w)) - { - - - *p++ = ((unsigned char)uut->VIDEO_B) << 4 | (unsigned char)uut->VIDEO_B; - *p++ = ((unsigned char)uut->VIDEO_G) << 4 | (unsigned char)uut->VIDEO_G; - *p++ = ((unsigned char)uut->VIDEO_R) << 4 | (unsigned char)uut->VIDEO_R; - p++; - //((((unsigned char)uut->VIDEO_G) & 0xc) << 1) | ((((unsigned char)uut->VIDEO_B) & 0xe) >> 1); - xcount++; - } - } - - - - main_time++; // Time passes... - } - - uut->final(); // Done simulating - // // (Though this example doesn't get here) - tfp->close(); - //Quit SDL - SDL_Quit(); - - delete uut; -} diff --git a/cores/archie/bench/rtl/archimedes_top_instrumented.v b/cores/archie/bench/rtl/archimedes_top_instrumented.v deleted file mode 100644 index 016462f..0000000 --- a/cores/archie/bench/rtl/archimedes_top_instrumented.v +++ /dev/null @@ -1,285 +0,0 @@ -`timescale 1ns / 1ps -// archimedes_top.v -// -// Archimedes top -// -// Copyright (c) 2014 Stephen J. Leary -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -/* version for instrumenting against arcem ioc */ -module archimedes_top_instrumented( - - // base CPU Clock - input CLKCPU_I, - input CLKPIX_I, - - input RESET_I, - - // cpu wishbone interface. - output MEM_CYC_O, - output MEM_STB_O, - output MEM_WE_O, - output ioc_cs, - output iospace, - - - input MEM_ACK_I, - input MEM_ERR_I, - input MEM_RTY_I, - - output [3:0] MEM_SEL_O, - output [2:0] MEM_CTI_O, - output [23:2] MEM_ADDR_O, - - input [31:0] MEM_DAT_I, - output [31:0] MEM_DAT_O, - - // video signals (VGA) - output HSYNC, - output VSYNC, - - output [3:0] VIDEO_R, - output [3:0] VIDEO_G, - output [3:0] VIDEO_B, - - input use_instrumented, - - input cpu_irq, - input cpu_firq, - - - - // "Floppy" LED - output DEBUG_LED, - - // connection to keyboard controller - output [7:0] KBD_OUT_DATA, - output KBD_OUT_STROBE, - input [7:0] KBD_IN_DATA, - input KBD_IN_STROBE - -); - -(*KEEP="TRUE"*)wire por_reset; - -// cpu bus -(*KEEP="TRUE"*)wire [31:0] cpu_address /* synthesis keep */; -(*KEEP="TRUE"*)wire [3:0] cpu_sel /* synthesis keep */ ; - - -(*KEEP="TRUE"*)wire cpu_spvmd/* synthesis keep */ ; -(*KEEP="TRUE"*)wire [31:0] cpu_dat_o/* synthesis keep */ ; -(*KEEP="TRUE"*)wire [31:0] cpu_dat_i/* synthesis keep */ ; - -(*KEEP="TRUE"*)wire cpu_cyc/* synthesis keep */ ; -(*KEEP="TRUE"*)wire cpu_stb/* synthesis keep */ ; -(*KEEP="TRUE"*)wire cpu_we/* synthesis keep */ ; - -(*KEEP="TRUE"*)wire cpu_ack/* synthesis keep */ ; -(*KEEP="TRUE"*)wire cpu_err/* synthesis keep */ ; -(*KEEP="TRUE"*)wire cpu_irq/* synthesis keep */ ; -(*KEEP="TRUE"*)wire cpu_firq/* synthesis keep */ ; - -// video DMA signals. -(*KEEP="TRUE"*)wire [31:0] vid_address; // VIDC D31-D0 -(*KEEP="TRUE"*)wire vid_flybk /* synthesis keep */; // VIDC FLYBK -(*KEEP="TRUE"*)wire vid_req; // VIDC REQ -(*KEEP="TRUE"*)wire vid_ack; // VIDC ACK - -//(*KEEP="TRUE"*)wire ioc_cs/* synthesis keep */ ; -//(*KEEP="TRUE"*)wire ioc_ack/* synthesis keep */ ; -(*KEEP="TRUE"*)wire [7:0] ioc_dat_o/* synthesis keep */ ; - -(*KEEP="TRUE"*)wire rom_low_cs/* synthesis keep */ ; -wire [5:0] ioc_cin, ioc_cout; - -a23_core ARM( - - .i_clk ( CLKCPU_I ), - - .o_wb_cyc ( cpu_cyc ), - .o_wb_stb ( cpu_stb ), - .o_wb_we ( cpu_we ), - - .o_wb_adr ( cpu_address ), - .o_wb_sel ( cpu_sel ), - - .i_wb_dat ( cpu_dat_i ), - .o_wb_dat ( cpu_dat_o ), - - - .i_wb_ack ( cpu_ack ), - .i_wb_err ( cpu_err ), - - .o_wb_tga ( cpu_spvmd ), - .i_irq ( cpu_irq ), - .i_firq ( cpu_firq ), - - .i_system_rdy(~por_reset ) -); - -memc MEMC( - - .clkcpu ( CLKCPU_I ), - .rst_i ( por_reset ), - - .spvmd (cpu_spvmd), - - // cpu interface - .cpu_address ( cpu_address[25:0] ), - .cpu_cyc ( cpu_cyc ), - .cpu_stb ( cpu_stb ), - .cpu_we ( cpu_we ), - .cpu_sel ( cpu_sel ), - .cpu_ack ( cpu_ack ), - .cpu_err ( cpu_err ), - - // memory interface - .mem_addr_o ( MEM_ADDR_O ), - .mem_stb_o ( MEM_STB_O ), - .mem_cyc_o ( MEM_CYC_O ), - .mem_ack_i ( MEM_ACK_I ), - .mem_sel_o ( MEM_SEL_O ), - .mem_we_o ( MEM_WE_O ), - .mem_cti_o ( MEM_CTI_O ), - - // vidc interface - .hsync ( HSYNC ), - .flybk ( vid_flybk ), - .vidrq ( vid_req ), - .vidak ( vid_ack ), - .sndak ( snd_ack ), - .sndrq ( snd_req ), - .vidw ( vid_we ), - - // ioc interface - .ioc_cs ( ioc_cs ), - .rom_low_cs ( rom_low_cs ), - .ram_cs ( ram_cs ), - - // irqs - - .sirq_n ( sirq_n ) -); - -i2cSlaveTop CMOS ( - .clk ( CLKCPU_I ), - .rst ( RESET_I ), - .sdaIn ( ioc_cout[0] ), - .sdaOut ( I2C_DIN ), - .scl ( ioc_cout[1] ) -); - - -vidc VIDC( - .clkpix2x(CLKPIX_I), - - .clkcpu(CLKCPU_I), - - .rst_i(por_reset), - - .cpu_dat(cpu_dat_o), - - // memc - .flybk ( vid_flybk ), - .vidak ( vid_ack ), - .vidrq ( vid_req ), - .sndak ( snd_ack ), - .sndrq ( snd_req ), - - .viddat ( MEM_DAT_I ), - .vidw ( vid_we ), - - // video signals - .hsync ( HSYNC ), - .vsync ( VSYNC ), - .video_r ( VIDEO_R ), - .video_g ( VIDEO_G ), - .video_b ( VIDEO_B ) -); - -ioc IOC( - - .clkcpu ( CLKCPU_I ), - .por ( por_reset ), - .ir ( vid_flybk ), - - .il ( {6'b1111, 1'b1, 1'b1 }), - - .c_in ( ioc_cin ), - .c_out ( ioc_cout ), - - // wishbone bus - .wb_adr ( cpu_address[6:2] ), - .wb_stb ( cpu_stb & cpu_address[21] & ioc_cs ), - .wb_cyc ( cpu_cyc & cpu_address[21] & ioc_cs ), - .wb_we ( cpu_we ), - //.wb_ack ( ioc_ack ), - - .wb_dat_i ( cpu_dat_o[23:16] ), - .wb_dat_o ( ioc_dat_o ), - .wb_bank ( cpu_address[18:16] ), - - //.irq ( cpu_irq ), - //.firq ( cpu_firq ), - - .kbd_out_data ( KBD_OUT_DATA ), - .kbd_out_strobe ( KBD_OUT_STROBE ), - .kbd_in_data ( KBD_IN_DATA ), - .kbd_in_strobe ( KBD_IN_STROBE ) -); - -por POR( - .clk ( CLKCPU_I ), - .rst_i ( RESET_I ), - .rst_o ( por_reset ) -); - - -reg [7:0] ext_latcha = 8'hFF; -wire ext_latcha_en = cpu_address == 26'h3350040 /* synthesis keep */ ; - -always @(posedge CLKCPU_I) begin - - if (ext_latcha_en & cpu_we & cpu_stb) begin - - ext_latcha <= cpu_dat_o[23:16]; - - end - -end - -assign iospace = ((cpu_address >= 26'h300_0000) & (cpu_address < 26'h380_0000)); -assign MEM_DAT_O = cpu_dat_o; -assign cpu_dat_i = (use_instrumented & iospace) ? MEM_DAT_I : - ioc_cs ? {ioc_dat_o, ioc_dat_o, ioc_dat_o, ioc_dat_o} : - ram_cs ? MEM_DAT_I : - 32'h0000_0000; - -assign ioc_cin[1:0] = {ioc_cout[1], I2C_DIN}; -assign ioc_cin[5:2] = ioc_cout[5:2]; - -assign DEBUG_LED = ~(~ext_latcha[6] & ~ext_latcha[0]); - -reg [63:0] clk_count = 0 ; - -always @(posedge CLKCPU_I) begin - - clk_count <= clk_count + 63'd1; - -end - -endmodule // archimedes_top diff --git a/cores/archie/bench/rtl/archimedes_top_nocpu.cpp b/cores/archie/bench/rtl/archimedes_top_nocpu.cpp deleted file mode 100644 index f357d7a..0000000 --- a/cores/archie/bench/rtl/archimedes_top_nocpu.cpp +++ /dev/null @@ -1,333 +0,0 @@ -#include // Defines common routines -#include "Varchimedes_top_nocpu.h" -#include "verilated_vcd_c.h" -#include -#include -#include -#include -#include -#include -#include - -Varchimedes_top_nocpu *uut; // Instantiation of module -unsigned int *main_memory = NULL; -unsigned int *rom_memory = NULL; - -struct cpuaccess -{ - signed char we; - unsigned int address; - unsigned int dat; - unsigned int be; // byte enable; - unsigned int expected; -}; - -vluint64_t main_time = 0; // Current simulation time -// This is a 64-bit integer to reduce wrap over issues and -// allow modulus. You can also use a double, if you wish. -double sc_time_stamp () { // Called by $time in Verilog - return main_time; // converts to double, to match - // what SystemC does -} - -void MEMAccess(struct cpuaccess* access) -{ - uut->cpu_address = access->address; - uut->cpu_we = (unsigned char) access->we; - uut->cpu_dat_o = access->dat; - uut->cpu_stb = 1; - uut->cpu_cyc = 1; - uut->cpu_sel = access->be; -} - -bool GetNextAccess(struct cpuaccess* access, std::istream& instream) -{ - bool result = false; - - std::string line; - - if (std::getline(instream,line)) - { - std::string cell; - std::stringstream lineStream(line); - - int x = sscanf(line.c_str(), "%i, 0x%x, 0x%x, 0x%x, %i", &(access->we), &(access->address), &(access->dat), &(access->be), &(access->expected)); - - /* - std::getline(lineStream, cell, ','); - access->we = atoi(cell.c_str()); - std::getline(lineStream, cell, ','); - std::stringstream ss; - ss << std::hex << cell; - ss >> access->address; - std::getline(lineStream, cell, ','); - ss.str(""); - ss.clear(); - ss << std::hex << cell; - ss >> access->dat; - std::getline(lineStream, cell, ','); - ss.str(""); - ss.clear(); - ss << std::hex << cell; - ss >> access->be; - std::getline(lineStream, cell, ','); - ss.str(""); - ss.clear(); - ss << std::hex << cell; - ss >> access->expected;*/ - result = true; - } - - return result; -} - -class Edge -{ -public: - Edge() - { - m_NegEdge = false; - m_PosEdge = false; - m_LastValue = false; - } - - void Update(bool value) - { - m_PosEdge = value & ~ m_LastValue; - m_NegEdge = ~value & m_LastValue; - m_LastValue = value; - } - - bool PosEdge() { return m_PosEdge; } - bool NegEdge() { return m_NegEdge; } - -private: - bool m_NegEdge; - bool m_PosEdge; - bool m_LastValue; -}; - -int main(int argc, char** argv) { - - int i = 0; - - cpuaccess* access = new cpuaccess; - - //The images - SDL_Surface* screen = NULL; - SDL_Init(SDL_INIT_VIDEO); - //Set up screen - screen = SDL_SetVideoMode( 800, 524, 32, SDL_SWSURFACE | SDL_RESIZABLE ); - - //Update Screen - SDL_Flip( screen ); - - // Check that the window was successfully made - if (screen == NULL) { - // In the event that the window could not be made... - printf("Could not create window: %s\n", SDL_GetError()); - return 1; - } - - // simulate a monitor - int screenwidth = 0; - int screenheight = 0; - - int xcount = 0; - int ycount = 0; - - Edge vsync; - Edge hsync; - Edge cpuclk; - Edge pixclk; - - main_memory = (unsigned int *) malloc(8*1024*1024); // 8MB of ram area. - rom_memory = main_memory + 1024*1024; - - std::string fileName = "../ROM310"; - if (argc > 1) - { - fileName = argv[1]; - } - - FILE *fp = fopen(fileName.c_str(), "r"); - if (fp == NULL) - { - std::cerr << "failed to open file" << std::endl; - exit(-1); - } - - std::cerr << fread(rom_memory, sizeof(char), 2*1024*1024, fp) << std::endl; - fclose(fp); - - Verilated::commandArgs(argc, argv); // Remember args - uut = new Varchimedes_top_nocpu; // Create instance - - Verilated::traceEverOn(true); - VerilatedVcdC* tfp = new VerilatedVcdC; - uut->trace(tfp, 99); - tfp->open("nocpu.vcd"); - - uut->RESET_I = 1; // Set some inputs - uut->cpu_spvmd = 1; - Uint8 *p = (Uint8 *)screen->pixels; - - int mem_wait_states = 0; - - while (!Verilated::gotFinish()) - { - if (main_time > 320) - { - uut->RESET_I = 0; // Deassert reset - } - - if ((main_time % 2) == 0) - { - uut->CLKCPU_I = uut->CLKCPU_I ? 0 : 1; // Toggle clock - } - - if ((main_time % 3) == 0) - { - uut->CLKPIX2X_I = uut->CLKPIX2X_I ? 0 : 1; // Toggle clock - } - - cpuclk.Update(uut->CLKCPU_I); - pixclk.Update(uut->CLKPIX2X_I); - vsync.Update(uut->VSYNC); - hsync.Update(uut->HSYNC); - - uut->eval(); // Evaluate model - - if (uut->MEM_STB_O && cpuclk.PosEdge() && !(bool)uut->MEM_ACK_I) - { - mem_wait_states++; - if (mem_wait_states > 0) - { - mem_wait_states = 0; - //std::cout << "MEM: " << std::hex << (uut->MEM_ADDR_O << 2) << std::endl; - - if (uut->MEM_WE_O) - { - unsigned int mask = 0; - if (uut->cpu_sel & 1) mask |= 0xFF; - if (uut->cpu_sel & 2) mask |= 0xFF00; - if (uut->cpu_sel & 4) mask |= 0xFF0000; - if (uut->cpu_sel & 8) mask |= 0xFF000000; - - if ((uut->MEM_ADDR_O << 2) > 4*1024*1024) - { - std::cerr << "Managed to write to ROM" << std::endl; - exit(-2); - } - - main_memory[uut->MEM_ADDR_O] = uut->MEM_DAT_O & mask | main_memory[uut->MEM_ADDR_O] & ~mask; - } - else - { - uut->MEM_DAT_I = main_memory[uut->MEM_ADDR_O]; - } - - uut->MEM_ACK_I = 1; - } - else - { - uut->MEM_ACK_I = 0; - } - - } - else if (cpuclk.PosEdge()) - { - uut->MEM_ACK_I = 0; - } - - if (cpuclk.PosEdge() && (uut->cpu_stb == 0) && (uut->RESET_I == 0)) - { - if (GetNextAccess(access, std::cin)) - { - MEMAccess(access); - } - else - { - std::cout << "finished instrumenting" << std::endl; - break; - } - } - else if (cpuclk.PosEdge() && (uut->cpu_ack)) - { - - - if (uut->cpu_we) - { - //std::cout << std::dec << main_time << ": " << i << ": write " << std::hex << uut->cpu_address << " data " << std::hex << uut->cpu_dat_o << " be " << (unsigned int) uut->cpu_sel << std::dec << std::endl; - } - else - { - //std::cout << std::dec << main_time << ": " << i << ": read " << std::hex << uut->cpu_address << " data " << std::hex << uut->cpu_dat_i << " expected " << std::hex << access->expected << std::dec << std::endl; - - if (access->expected != uut->cpu_dat_i) - { - std::cout << "Incorrect result on read" << std:: endl; - break; - } - } - - uut->cpu_stb = 0; - uut->cpu_cyc = 0; - i++; - } - else if (cpuclk.PosEdge() && (uut->cpu_err)) - { - std::cout << "Unexpected data abort address:" << std::hex << uut->cpu_address << std::endl; - break; - } - - - if (vsync.PosEdge()) - { - SDL_Flip( screen ); - p = (Uint8 *)screen->pixels; - - std::cerr << ycount << std::endl; - ycount = 0; - xcount = 0; - - } - else if (hsync.PosEdge()) - { - //std::cerr << xcount << std::endl; - ycount++; - xcount = 0; - // std::cerr << (uut->VSYNC ? true : false) << " sync: xcount " << xcount << " ycount " << ycount << std::endl; - //SDL_Flip( screen ); - p = (Uint8 *)screen->pixels; - p+= ycount * screen->w *4; - } - - else if (pixclk.PosEdge() && (bool)uut->VSYNC && (bool) uut->HSYNC) - { - if ((ycount < screen->h) && (xcount <= screen->w)) - { - - - *p++ = ((unsigned char)uut->VIDEO_B) << 4 | (unsigned char)uut->VIDEO_B; - *p++ = ((unsigned char)uut->VIDEO_G) << 4 | (unsigned char)uut->VIDEO_G; - *p++ = ((unsigned char)uut->VIDEO_R) << 4 | (unsigned char)uut->VIDEO_R; - p++; - //((((unsigned char)uut->VIDEO_G) & 0xc) << 1) | ((((unsigned char)uut->VIDEO_B) & 0xe) >> 1); - xcount++; - } - } - - - //tfp->dump (main_time); - main_time++; // Time passes... - } - - uut->final(); // Done simulating - // // (Though this example doesn't get here) - - //Quit SDL - SDL_Quit(); - - delete uut; -} diff --git a/cores/archie/bench/rtl/archimedes_top_nocpu.v b/cores/archie/bench/rtl/archimedes_top_nocpu.v deleted file mode 100644 index 6951ad9..0000000 --- a/cores/archie/bench/rtl/archimedes_top_nocpu.v +++ /dev/null @@ -1,353 +0,0 @@ -`timescale 1ns / 1ps -// archimedes_top.v -// -// Archimedes top -// -// Copyright (c) 2014 Stephen J. Leary -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -module archimedes_top_nocpu( - - // base CPU Clock - input CLKCPU_I, - input CLKPIX2X_I, - output CLKPIX_O, - - input RESET_I, - - // cpu wishbone interface. - output MEM_CYC_O, - output MEM_STB_O, - output MEM_WE_O, - - input MEM_ACK_I, - input MEM_ERR_I, - input MEM_RTY_I, - - output [3:0] MEM_SEL_O, - output [2:0] MEM_CTI_O, - output [23:2] MEM_ADDR_O, - - input [31:0] MEM_DAT_I, - output [31:0] MEM_DAT_O, - - // dummy cpu - - // cpu bus. - input cpu_we, - input cpu_spvmd, - input cpu_stb, - input cpu_cyc, - output cpu_err /* synthesis keep */ , - output cpu_ack, - - input [31:0] cpu_dat_o, - output[31:0] cpu_dat_i, - input [25:0] cpu_address, - input [3:0] cpu_sel, - - // video signals (VGA) - output HSYNC, - output VSYNC, - - output [3:0] VIDEO_R, - output [3:0] VIDEO_G, - output [3:0] VIDEO_B, - - // VIDC Enhancer selection. - // These are from external latch C - output [1:0] VIDBASECLK_O, - output [1:0] VIDSYNCPOL_O, - - // I2C bus to the CMOS. - output I2C_DOUT, - input I2C_DIN, - output I2C_CLOCK, - - // "Floppy" LED - output DEBUG_LED, - - // floppy connections to external controller - output [31:0] FDC_DIO_STATUS, - input [7:0] FDC_DIN, - input FDC_DIN_STROBE, - - // connection to keyboard controller - output [7:0] KBD_OUT_DATA, - output KBD_OUT_STROBE, - input [7:0] KBD_IN_DATA, - input KBD_IN_STROBE, - - input [4:0] JOYSTICK0, - input [4:0] JOYSTICK1 - -); - -(*KEEP="TRUE"*)wire por_reset; - - -(*KEEP="TRUE"*)wire cpu_irq/* synthesis keep */ ; -(*KEEP="TRUE"*)wire cpu_firq/* synthesis keep */ ; - -// video DMA signals. -(*KEEP="TRUE"*)wire [31:0] vid_address; // VIDC D31-D0 -(*KEEP="TRUE"*)wire vid_flybk /* synthesis keep */; // VIDC FLYBK -(*KEEP="TRUE"*)wire vid_req; // VIDC REQ -(*KEEP="TRUE"*)wire vid_ack; // VIDC ACK - -(*KEEP="TRUE"*)wire ioc_cs/* synthesis keep */ ; -(*KEEP="TRUE"*)wire ioc_ack/* synthesis keep */ ; -(*KEEP="TRUE"*)wire [7:0] ioc_dat_o/* synthesis keep */ ; - -(*KEEP="TRUE"*)wire rom_low_cs/* synthesis keep */ ; -wire [5:0] ioc_cin, ioc_cout; - -memc MEMC( - - .clkcpu ( CLKCPU_I ), - .rst_i ( por_reset ), - - .spvmd (cpu_spvmd), - - // cpu interface - .cpu_address ( cpu_address[25:0] ), - .cpu_cyc ( cpu_cyc ), - .cpu_stb ( cpu_stb ), - .cpu_we ( cpu_we ), - .cpu_sel ( cpu_sel ), - .cpu_ack ( cpu_ack ), - .cpu_err ( cpu_err ), - - // memory interface - .mem_addr_o ( MEM_ADDR_O ), - .mem_stb_o ( MEM_STB_O ), - .mem_cyc_o ( MEM_CYC_O ), - .mem_ack_i ( MEM_ACK_I ), - .mem_sel_o ( MEM_SEL_O ), - .mem_we_o ( MEM_WE_O ), - .mem_cti_o ( MEM_CTI_O ), - - // vidc interface - .hsync ( HSYNC ), - .flybk ( vid_flybk ), - .vidrq ( vid_req ), - .vidak ( vid_ack ), - .sndak ( snd_ack ), - .sndrq ( snd_req ), - .vidw ( vid_we ), - - // ioc interface - .ioc_cs ( ioc_cs ), - .rom_low_cs ( rom_low_cs ), - .ram_cs ( ram_cs ), - - // irqs - - .sirq_n ( sirq_n ) -); - -vidc VIDC( - - .clkpix2x ( CLKPIX2X_I ), - .clkpix ( CLKPIX_O ), - .clkcpu ( CLKCPU_I ), - - .rst_i(por_reset), - - .cpu_dat(cpu_dat_o), - - // memc - .flybk ( vid_flybk ), - .vidak ( vid_ack ), - .vidrq ( vid_req ), - .sndak ( snd_ack ), - .sndrq ( snd_req ), - - .viddat ( MEM_DAT_I ), - .vidw ( vid_we ), - - // video signals - .hsync ( HSYNC ), - .vsync ( VSYNC ), - .video_r ( VIDEO_R ), - .video_g ( VIDEO_G ), - .video_b ( VIDEO_B ) -); - -wire [1:0] ioc_speed = cpu_address[20:19]; -wire [7:1] ioc_select; -wire ioc_sext; -// podule data bus. -wire [15:0] pod_dat_o; -wire [15:0] pod_dat_i; - -wire floppy_firq; -wire floppy_drq; - -ioc IOC( - - .clkcpu ( CLKCPU_I ), - .clk2m_en ( ioc_clk2m_en ), - .clk8m_en ( ioc_clk8m_en ), - - .por ( por_reset ), - .ir ( vid_flybk ), - - .fh ( {floppy_firq, floppy_drq}), - - .il ( {6'b1111, sirq_n, 1'b1 }), - - .c_in ( ioc_cin ), - .c_out ( ioc_cout ), - - .select ( ioc_select ), - .sext ( ioc_sext ), - - // wishbone bus - .wb_adr ( cpu_address[6:2] ), - .wb_stb ( cpu_stb & cpu_address[21] & ioc_cs ), - .wb_cyc ( cpu_cyc & cpu_address[21] & ioc_cs ), - .wb_we ( cpu_we ), - - .wb_dat_i ( cpu_dat_o[23:16] ), - .wb_dat_o ( ioc_dat_o ), - .wb_bank ( cpu_address[18:16] ), - - .irq ( cpu_irq ), - .firq ( cpu_firq ), - - .kbd_out_data ( KBD_OUT_DATA ), - .kbd_out_strobe ( KBD_OUT_STROBE ), - .kbd_in_data ( KBD_IN_DATA ), - .kbd_in_strobe ( KBD_IN_STROBE ) -); - -wire podules_en = ioc_cs & ioc_select[4]; - -// all podules live in the the podules module. -// this is just to keep things tidy. -podules PODULES( - // everything is synced to the master 32m clock except the pix clock. - .clkcpu ( CLKCPU_I ), - .clk2m_en ( ioc_clk2m_en ), - .clk8m_en ( ioc_clk8m_en ), - - .rst_i ( RESET_I ), - - .speed_i ( ioc_speed ), - - .wb_cyc ( cpu_cyc & podules_en), - .wb_stb ( cpu_stb & podules_en), - .wb_we ( cpu_we & podules_en), - - .wb_dat_o ( pod_dat_o ), - .wb_dat_i ( cpu_dat_o[15:0] ), - .wb_adr ( cpu_address[15:2] ) -); - -wire [7:0] floppy_dat_o; -wire floppy_en = ioc_cs & ioc_select[1]; - -// floppy drive signals. -wire [3:0] floppy_drive; -wire floppy_side; -wire floppy_motor; -wire floppy_inuse; -wire floppy_density; -wire floppy_reset; - -fdc1772 FDC1772 ( - - .clkcpu ( CLKCPU_I ), - .clk8m_en ( ioc_clk8m_en ), - - .wb_cyc ( cpu_cyc & floppy_en ), - .wb_stb ( cpu_stb & floppy_en ), - .wb_we ( cpu_we & floppy_en ), - - .wb_dat_o ( floppy_dat_o ), - .wb_dat_i ( cpu_dat_o[23:16] ), - .wb_adr ( cpu_address[15:2] ), - - .floppy_firq ( floppy_firq ), - .floppy_drq ( floppy_drq ), - - .dio_status ( FDC_DIO_STATUS ), - .dio_in_strobe ( FDC_DIN_STROBE ), - .dio_in ( FDC_DIN ), - - .floppy_drive ( floppy_drive ), - .floppy_motor ( floppy_motor ), - .floppy_inuse ( floppy_inuse ), - .floppy_side ( floppy_side ), - .floppy_density ( floppy_density ), - .floppy_reset ( floppy_reset ) - -); - -wire [7:0] latches_dat_o; -wire latches_en = ioc_cs & ioc_select[5] & (ioc_speed == 2'd2); - -latches LATCHES( - - .clkcpu ( CLKCPU_I ), - - .wb_cyc ( cpu_cyc & latches_en ), - .wb_stb ( cpu_stb & latches_en ), - .wb_we ( cpu_we & latches_en ), - - .wb_dat_i ( cpu_dat_o[23:16] ), - .wb_dat_o ( latches_dat_o ), - .wb_adr ( cpu_address[15:2] ), - - .floppy_drive ( floppy_drive ), - .floppy_motor ( floppy_motor ), - .floppy_inuse ( floppy_inuse ), - .floppy_side ( floppy_side ), - .floppy_density ( floppy_density ), - .floppy_reset ( floppy_reset ), - - .joy0 ( JOYSTICK0 ), - .joy1 ( JOYSTICK1 ), - - .baseclk ( VIDBASECLK_O ), - .syncpol ( VIDSYNCPOL_O ) -); - -por POR( - .clk ( CLKCPU_I ), - .rst_i ( RESET_I ), - .rst_o ( por_reset ) -); - - -assign MEM_DAT_O = cpu_dat_o; - -assign cpu_dat_i = floppy_en ? {24'd0, floppy_dat_o} : - latches_en ? {24'd0, latches_dat_o} : - podules_en ? {16'd0, pod_dat_o} : - ioc_cs & ~ioc_sext ? {24'd0, ioc_dat_o} : - ram_cs ? MEM_DAT_I : - 32'hFFFF_FFFF; - -assign I2C_CLOCK = ioc_cout[1]; -assign I2C_DOUT = ioc_cout[0]; - -assign ioc_cin[5:0] = {ioc_cout[5:2], I2C_CLOCK, I2C_DIN}; -assign DEBUG_LED = ~(~floppy_inuse & ~floppy_drive[0]); - - -endmodule // archimedes_top diff --git a/cores/archie/bench/rtl/debug_functions.v b/cores/archie/bench/rtl/debug_functions.v deleted file mode 100644 index e63cdee..0000000 --- a/cores/archie/bench/rtl/debug_functions.v +++ /dev/null @@ -1,228 +0,0 @@ -////////////////////////////////////////////////////////////////// -// // -// Debug Functions // -// // -// This file is part of the Amber project // -// http://www.opencores.org/project,amber // -// // -// Description // -// A bunch of non-synthesizable testbench functions // -// // -// Author(s): // -// - Conor Santifort, csantifort.amber@gmail.com // -// // -////////////////////////////////////////////////////////////////// -// // -// Copyright (C) 2010 Authors and OPENCORES.ORG // -// // -// This source file may be used and distributed without // -// restriction provided that this copyright statement is not // -// removed from the file and that any derivative work contains // -// the original copyright notice and the associated disclaimer. // -// // -// This source file is free software; you can redistribute it // -// and/or modify it under the terms of the GNU Lesser General // -// Public License as published by the Free Software Foundation; // -// either version 2.1 of the License, or (at your option) any // -// later version. // -// // -// This source is distributed in the hope that it will be // -// useful, but WITHOUT ANY WARRANTY; without even the implied // -// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // -// PURPOSE. See the GNU Lesser General Public License for more // -// details. // -// // -// You should have received a copy of the GNU Lesser General // -// Public License along with this source; if not, download it // -// from http://www.opencores.org/lgpl.shtml // -// // -////////////////////////////////////////////////////////////////// - -// Testbench Functions used in more than one module - - -function [31:0] hex_chars_to_32bits; -input [8*8-1:0] hex_chars; -begin -hex_chars_to_32bits[31:28] = hex_chars_to_4bits (hex_chars[8*8-1:7*8]); -hex_chars_to_32bits[27:24] = hex_chars_to_4bits (hex_chars[7*8-1:6*8]); -hex_chars_to_32bits[23:20] = hex_chars_to_4bits (hex_chars[6*8-1:5*8]); -hex_chars_to_32bits[19:16] = hex_chars_to_4bits (hex_chars[5*8-1:4*8]); -hex_chars_to_32bits[15:12] = hex_chars_to_4bits (hex_chars[4*8-1:3*8]); -hex_chars_to_32bits[11: 8] = hex_chars_to_4bits (hex_chars[3*8-1:2*8]); -hex_chars_to_32bits[ 7: 4] = hex_chars_to_4bits (hex_chars[2*8-1:1*8]); -hex_chars_to_32bits[ 3: 0] = hex_chars_to_4bits (hex_chars[1*8-1: 0]); -end -endfunction - - -function [7:0] hex_chars_to_8bits; -input [8*2-1:0] hex_chars; -begin -hex_chars_to_8bits[ 7: 4] = hex_chars_to_4bits (hex_chars[2*8-1:1*8]); -hex_chars_to_8bits[ 3: 0] = hex_chars_to_4bits (hex_chars[1*8-1: 0]); -end -endfunction - - -function [3:0] hex_chars_to_4bits; -input [7:0] hex_chars; -begin -case (hex_chars) - "0" : hex_chars_to_4bits = 4'h0; - "1" : hex_chars_to_4bits = 4'h1; - "2" : hex_chars_to_4bits = 4'h2; - "3" : hex_chars_to_4bits = 4'h3; - "4" : hex_chars_to_4bits = 4'h4; - "5" : hex_chars_to_4bits = 4'h5; - "6" : hex_chars_to_4bits = 4'h6; - "7" : hex_chars_to_4bits = 4'h7; - "8" : hex_chars_to_4bits = 4'h8; - "9" : hex_chars_to_4bits = 4'h9; - "a" : hex_chars_to_4bits = 4'ha; - "b" : hex_chars_to_4bits = 4'hb; - "c" : hex_chars_to_4bits = 4'hc; - "d" : hex_chars_to_4bits = 4'hd; - "e" : hex_chars_to_4bits = 4'he; - "f" : hex_chars_to_4bits = 4'hf; - "A" : hex_chars_to_4bits = 4'ha; - "B" : hex_chars_to_4bits = 4'hb; - "C" : hex_chars_to_4bits = 4'hc; - "D" : hex_chars_to_4bits = 4'hd; - "E" : hex_chars_to_4bits = 4'he; - "F" : hex_chars_to_4bits = 4'hf; -endcase -end -endfunction - - -function [120*8-1:0] align_line; -input [120*8-1:0] line; -begin -case (1'd1) - line[1 *8-1: 0] == 8'd0 : align_line = 960'd0; - line[2 *8-1:1 *8] == 8'd0 : align_line = {line[1 *8-1: 0], 952'd0}; - line[3 *8-1:2 *8] == 8'd0 : align_line = {line[2 *8-1: 0], 944'd0}; - line[4 *8-1:3 *8] == 8'd0 : align_line = {line[3 *8-1: 0], 936'd0}; - line[5 *8-1:4 *8] == 8'd0 : align_line = {line[4 *8-1: 0], 928'd0}; - line[6 *8-1:5 *8] == 8'd0 : align_line = {line[5 *8-1: 0], 920'd0}; - line[7 *8-1:6 *8] == 8'd0 : align_line = {line[6 *8-1: 0], 912'd0}; - line[8 *8-1:7 *8] == 8'd0 : align_line = {line[7 *8-1: 0], 904'd0}; - line[9 *8-1:8 *8] == 8'd0 : align_line = {line[8 *8-1: 0], 896'd0}; - line[10 *8-1:9 *8] == 8'd0 : align_line = {line[9 *8-1: 0], 888'd0}; - line[11 *8-1:10 *8] == 8'd0 : align_line = {line[10 *8-1: 0], 880'd0}; - line[12 *8-1:11 *8] == 8'd0 : align_line = {line[11 *8-1: 0], 872'd0}; - line[13 *8-1:12 *8] == 8'd0 : align_line = {line[12 *8-1: 0], 864'd0}; - line[14 *8-1:13 *8] == 8'd0 : align_line = {line[13 *8-1: 0], 856'd0}; - line[15 *8-1:14 *8] == 8'd0 : align_line = {line[14 *8-1: 0], 848'd0}; - line[16 *8-1:15 *8] == 8'd0 : align_line = {line[15 *8-1: 0], 840'd0}; - line[17 *8-1:16 *8] == 8'd0 : align_line = {line[16 *8-1: 0], 832'd0}; - line[18 *8-1:17 *8] == 8'd0 : align_line = {line[17 *8-1: 0], 824'd0}; - line[19 *8-1:18 *8] == 8'd0 : align_line = {line[18 *8-1: 0], 816'd0}; - line[20 *8-1:19 *8] == 8'd0 : align_line = {line[19 *8-1: 0], 808'd0}; - line[21 *8-1:20 *8] == 8'd0 : align_line = {line[20 *8-1: 0], 800'd0}; - line[22 *8-1:21 *8] == 8'd0 : align_line = {line[21 *8-1: 0], 792'd0}; - line[23 *8-1:22 *8] == 8'd0 : align_line = {line[22 *8-1: 0], 784'd0}; - line[24 *8-1:23 *8] == 8'd0 : align_line = {line[23 *8-1: 0], 776'd0}; - line[25 *8-1:24 *8] == 8'd0 : align_line = {line[24 *8-1: 0], 768'd0}; - line[26 *8-1:25 *8] == 8'd0 : align_line = {line[25 *8-1: 0], 760'd0}; - line[27 *8-1:26 *8] == 8'd0 : align_line = {line[26 *8-1: 0], 752'd0}; - line[28 *8-1:27 *8] == 8'd0 : align_line = {line[27 *8-1: 0], 744'd0}; - line[29 *8-1:28 *8] == 8'd0 : align_line = {line[28 *8-1: 0], 736'd0}; - line[30 *8-1:29 *8] == 8'd0 : align_line = {line[29 *8-1: 0], 728'd0}; - line[31 *8-1:30 *8] == 8'd0 : align_line = {line[30 *8-1: 0], 720'd0}; - line[32 *8-1:31 *8] == 8'd0 : align_line = {line[31 *8-1: 0], 712'd0}; - line[33 *8-1:32 *8] == 8'd0 : align_line = {line[32 *8-1: 0], 704'd0}; - line[34 *8-1:33 *8] == 8'd0 : align_line = {line[33 *8-1: 0], 696'd0}; - line[35 *8-1:34 *8] == 8'd0 : align_line = {line[34 *8-1: 0], 688'd0}; - line[36 *8-1:35 *8] == 8'd0 : align_line = {line[35 *8-1: 0], 680'd0}; - line[37 *8-1:36 *8] == 8'd0 : align_line = {line[36 *8-1: 0], 672'd0}; - line[38 *8-1:37 *8] == 8'd0 : align_line = {line[37 *8-1: 0], 664'd0}; - line[39 *8-1:38 *8] == 8'd0 : align_line = {line[38 *8-1: 0], 656'd0}; - line[40 *8-1:39 *8] == 8'd0 : align_line = {line[39 *8-1: 0], 648'd0}; - line[41 *8-1:40 *8] == 8'd0 : align_line = {line[40 *8-1: 0], 640'd0}; - line[42 *8-1:41 *8] == 8'd0 : align_line = {line[41 *8-1: 0], 632'd0}; - line[43 *8-1:42 *8] == 8'd0 : align_line = {line[42 *8-1: 0], 624'd0}; - line[44 *8-1:43 *8] == 8'd0 : align_line = {line[43 *8-1: 0], 616'd0}; - line[45 *8-1:44 *8] == 8'd0 : align_line = {line[44 *8-1: 0], 608'd0}; - line[46 *8-1:45 *8] == 8'd0 : align_line = {line[45 *8-1: 0], 600'd0}; - line[47 *8-1:46 *8] == 8'd0 : align_line = {line[46 *8-1: 0], 592'd0}; - line[48 *8-1:47 *8] == 8'd0 : align_line = {line[47 *8-1: 0], 584'd0}; - line[49 *8-1:48 *8] == 8'd0 : align_line = {line[48 *8-1: 0], 576'd0}; - line[50 *8-1:49 *8] == 8'd0 : align_line = {line[49 *8-1: 0], 568'd0}; - line[51 *8-1:50 *8] == 8'd0 : align_line = {line[50 *8-1: 0], 560'd0}; - line[52 *8-1:51 *8] == 8'd0 : align_line = {line[51 *8-1: 0], 552'd0}; - line[53 *8-1:52 *8] == 8'd0 : align_line = {line[52 *8-1: 0], 544'd0}; - line[54 *8-1:53 *8] == 8'd0 : align_line = {line[53 *8-1: 0], 536'd0}; - line[55 *8-1:54 *8] == 8'd0 : align_line = {line[54 *8-1: 0], 528'd0}; - line[56 *8-1:55 *8] == 8'd0 : align_line = {line[55 *8-1: 0], 520'd0}; - line[57 *8-1:56 *8] == 8'd0 : align_line = {line[56 *8-1: 0], 512'd0}; - line[58 *8-1:57 *8] == 8'd0 : align_line = {line[57 *8-1: 0], 504'd0}; - line[59 *8-1:58 *8] == 8'd0 : align_line = {line[58 *8-1: 0], 496'd0}; - line[60 *8-1:59 *8] == 8'd0 : align_line = {line[59 *8-1: 0], 488'd0}; - line[61 *8-1:60 *8] == 8'd0 : align_line = {line[60 *8-1: 0], 480'd0}; - line[62 *8-1:61 *8] == 8'd0 : align_line = {line[61 *8-1: 0], 472'd0}; - line[63 *8-1:62 *8] == 8'd0 : align_line = {line[62 *8-1: 0], 464'd0}; - line[64 *8-1:63 *8] == 8'd0 : align_line = {line[63 *8-1: 0], 456'd0}; - line[65 *8-1:64 *8] == 8'd0 : align_line = {line[64 *8-1: 0], 448'd0}; - line[66 *8-1:65 *8] == 8'd0 : align_line = {line[65 *8-1: 0], 440'd0}; - line[67 *8-1:66 *8] == 8'd0 : align_line = {line[66 *8-1: 0], 432'd0}; - line[68 *8-1:67 *8] == 8'd0 : align_line = {line[67 *8-1: 0], 424'd0}; - line[69 *8-1:68 *8] == 8'd0 : align_line = {line[68 *8-1: 0], 416'd0}; - line[70 *8-1:69 *8] == 8'd0 : align_line = {line[69 *8-1: 0], 408'd0}; - line[71 *8-1:70 *8] == 8'd0 : align_line = {line[70 *8-1: 0], 400'd0}; - line[72 *8-1:71 *8] == 8'd0 : align_line = {line[71 *8-1: 0], 392'd0}; - line[73 *8-1:72 *8] == 8'd0 : align_line = {line[72 *8-1: 0], 384'd0}; - line[74 *8-1:73 *8] == 8'd0 : align_line = {line[73 *8-1: 0], 376'd0}; - line[75 *8-1:74 *8] == 8'd0 : align_line = {line[74 *8-1: 0], 368'd0}; - line[76 *8-1:75 *8] == 8'd0 : align_line = {line[75 *8-1: 0], 360'd0}; - line[77 *8-1:76 *8] == 8'd0 : align_line = {line[76 *8-1: 0], 352'd0}; - line[78 *8-1:77 *8] == 8'd0 : align_line = {line[77 *8-1: 0], 344'd0}; - line[79 *8-1:78 *8] == 8'd0 : align_line = {line[78 *8-1: 0], 336'd0}; - line[80 *8-1:79 *8] == 8'd0 : align_line = {line[79 *8-1: 0], 328'd0}; - line[81 *8-1:80 *8] == 8'd0 : align_line = {line[80 *8-1: 0], 320'd0}; - line[82 *8-1:81 *8] == 8'd0 : align_line = {line[81 *8-1: 0], 312'd0}; - line[83 *8-1:82 *8] == 8'd0 : align_line = {line[82 *8-1: 0], 304'd0}; - line[84 *8-1:83 *8] == 8'd0 : align_line = {line[83 *8-1: 0], 296'd0}; - line[85 *8-1:84 *8] == 8'd0 : align_line = {line[84 *8-1: 0], 288'd0}; - line[86 *8-1:85 *8] == 8'd0 : align_line = {line[85 *8-1: 0], 280'd0}; - line[87 *8-1:86 *8] == 8'd0 : align_line = {line[86 *8-1: 0], 272'd0}; - line[88 *8-1:87 *8] == 8'd0 : align_line = {line[87 *8-1: 0], 264'd0}; - line[89 *8-1:88 *8] == 8'd0 : align_line = {line[88 *8-1: 0], 256'd0}; - line[90 *8-1:89 *8] == 8'd0 : align_line = {line[89 *8-1: 0], 248'd0}; - line[91 *8-1:90 *8] == 8'd0 : align_line = {line[90 *8-1: 0], 240'd0}; - line[92 *8-1:91 *8] == 8'd0 : align_line = {line[91 *8-1: 0], 232'd0}; - line[93 *8-1:92 *8] == 8'd0 : align_line = {line[92 *8-1: 0], 224'd0}; - line[94 *8-1:93 *8] == 8'd0 : align_line = {line[93 *8-1: 0], 216'd0}; - line[95 *8-1:94 *8] == 8'd0 : align_line = {line[94 *8-1: 0], 208'd0}; - line[96 *8-1:95 *8] == 8'd0 : align_line = {line[95 *8-1: 0], 200'd0}; - line[97 *8-1:96 *8] == 8'd0 : align_line = {line[96 *8-1: 0], 192'd0}; - line[98 *8-1:97 *8] == 8'd0 : align_line = {line[97 *8-1: 0], 184'd0}; - line[99 *8-1:98 *8] == 8'd0 : align_line = {line[98 *8-1: 0], 176'd0}; - line[100*8-1:99 *8] == 8'd0 : align_line = {line[99 *8-1: 0], 168'd0}; - line[101*8-1:100*8] == 8'd0 : align_line = {line[100*8-1: 0], 160'd0}; - line[102*8-1:101*8] == 8'd0 : align_line = {line[101*8-1: 0], 152'd0}; - line[103*8-1:102*8] == 8'd0 : align_line = {line[102*8-1: 0], 144'd0}; - line[104*8-1:103*8] == 8'd0 : align_line = {line[103*8-1: 0], 136'd0}; - line[105*8-1:104*8] == 8'd0 : align_line = {line[104*8-1: 0], 128'd0}; - line[106*8-1:105*8] == 8'd0 : align_line = {line[105*8-1: 0], 120'd0}; - line[107*8-1:106*8] == 8'd0 : align_line = {line[106*8-1: 0], 112'd0}; - line[108*8-1:107*8] == 8'd0 : align_line = {line[107*8-1: 0], 104'd0}; - line[109*8-1:108*8] == 8'd0 : align_line = {line[108*8-1: 0], 96'd0}; - line[110*8-1:109*8] == 8'd0 : align_line = {line[109*8-1: 0], 88'd0}; - line[111*8-1:110*8] == 8'd0 : align_line = {line[110*8-1: 0], 80'd0}; - line[112*8-1:111*8] == 8'd0 : align_line = {line[111*8-1: 0], 72'd0}; - line[113*8-1:112*8] == 8'd0 : align_line = {line[112*8-1: 0], 64'd0}; - line[114*8-1:113*8] == 8'd0 : align_line = {line[113*8-1: 0], 56'd0}; - line[115*8-1:114*8] == 8'd0 : align_line = {line[114*8-1: 0], 48'd0}; - line[116*8-1:115*8] == 8'd0 : align_line = {line[115*8-1: 0], 40'd0}; - line[117*8-1:116*8] == 8'd0 : align_line = {line[116*8-1: 0], 32'd0}; - line[118*8-1:117*8] == 8'd0 : align_line = {line[117*8-1: 0], 24'd0}; - line[119*8-1:118*8] == 8'd0 : align_line = {line[118*8-1: 0], 16'd0}; - line[120*8-1:119*8] == 8'd0 : align_line = {line[119*8-1: 0], 8'd0}; - - default: align_line = 960'd0; -endcase -end -endfunction - diff --git a/cores/archie/bench/rtl/fakedata_io.v b/cores/archie/bench/rtl/fakedata_io.v deleted file mode 100644 index 61313a4..0000000 --- a/cores/archie/bench/rtl/fakedata_io.v +++ /dev/null @@ -1,96 +0,0 @@ -`timescale 1ns / 1ps -/* - Copyright (c) 2012-2014, Stephen J. Leary - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -module fakedata_io #(parameter ADDR_WIDTH=24, START_ADDR = 0) ( - // io controller spi interface - input rst, - input sck, - input ss, - input sdi, - - output downloading, // signal indicating an active download - output [ADDR_WIDTH-1:0] size, // number of bytes in input buffer - - // external ram interface - input clk, - output reg wr, - output reg [ADDR_WIDTH-1:0] a, - output [3:0] sel, - output [31:0] d -); - - wire [7:0] data = 8'd0; - - -assign sel = a[1:0] == 2'b00 ? 4'b0001 : - a[1:0] == 2'b01 ? 4'b0010 : - a[1:0] == 2'b10 ? 4'b0100 : 4'b1000; - -assign d = {data,data,data,data}; -reg [4:0] count = 0; -initial begin - - - //$readmemh("desktop.mif", mem); - -end - - -always @(posedge clk) begin - - if (rst) begin - - a <= 0; - count <= 0; - wr <= 1'b0; - - end else begin - - wr <= 1'b0; - - if (downloading) begin - - count <= count + 5'd1; - - if (count == 5'h00) begin - wr <= 1'b1; - end else if (count == 5'h1f) begin - - - a <= a + 23'd1; - - end - end - - end - -end - -assign downloading = 0; - -endmodule diff --git a/cores/archie/bench/rtl/global_defines.v b/cores/archie/bench/rtl/global_defines.v deleted file mode 100644 index 4d298e7..0000000 --- a/cores/archie/bench/rtl/global_defines.v +++ /dev/null @@ -1,95 +0,0 @@ -////////////////////////////////////////////////////////////////// -// // -// Global testbench defines // -// // -// This file is part of the Amber project // -// http://www.opencores.org/project,amber // -// // -// Description // -// Contains a set of defines for each module so if the module // -// hierarchy changes, hierarchical references to signals // -// will still work as long as this file is updated. // -// // -// Author(s): // -// - Conor Santifort, csantifort.amber@gmail.com // -// // -////////////////////////////////////////////////////////////////// -// // -// Copyright (C) 2010 Authors and OPENCORES.ORG // -// // -// This source file may be used and distributed without // -// restriction provided that this copyright statement is not // -// removed from the file and that any derivative work contains // -// the original copyright notice and the associated disclaimer. // -// // -// This source file is free software; you can redistribute it // -// and/or modify it under the terms of the GNU Lesser General // -// Public License as published by the Free Software Foundation; // -// either version 2.1 of the License, or (at your option) any // -// later version. // -// // -// This source is distributed in the hope that it will be // -// useful, but WITHOUT ANY WARRANTY; without even the implied // -// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // -// PURPOSE. See the GNU Lesser General Public License for more // -// details. // -// // -// You should have received a copy of the GNU Lesser General // -// Public License along with this source; if not, download it // -// from http://www.opencores.org/lgpl.shtml // -// // -////////////////////////////////////////////////////////////////// - -// --------------------------------------------------------------- -// Module hierarchy defines -// --------------------------------------------------------------- -`ifndef _GLOBAL_DEFINES -`define _GLOBAL_DEFINES - -`ifndef AMBER_TIMEOUT - `define AMBER_TIMEOUT 0 -`endif - -`ifndef U_TB -`define U_TB a23_core -`define U_SYSTEM a23_core -`define U_AMBER a23_core -`endif - -`define U_FETCH `U_AMBER.u_fetch -`define U_MMU `U_FETCH.u_mmu -`define U_CACHE `U_FETCH.u_cache -`define U_COPRO15 `U_AMBER.u_coprocessor -`define U_EXECUTE `U_AMBER.u_execute -`define U_WB `U_AMBER.u_write_back -`define U_REGISTER_BANK `U_EXECUTE.u_register_bank -`define U_DECODE `U_AMBER.u_decode -`define U_DECOMPILE `U_DECODE.u_decompile -`define U_L2CACHE `U_SYSTEM.u_l2cache -`define U_TEST_MODULE `U_SYSTEM.u_test_module - -`ifdef AMBER_A25_CORE - `define U_MEM `U_AMBER.u_mem - `define U_DCACHE `U_MEM.u_dcache - `define U_WISHBONE `U_AMBER.u_wishbone - `define U_BOOT_MEM `U_SYSTEM.boot_mem128.u_boot_mem -`else - `define U_WISHBONE `U_FETCH.u_wishbone - `define U_BOOT_MEM `U_SYSTEM.boot_mem32.u_boot_mem -`endif -// --------------------------------------------------------------- - -`define TB_DEBUG_MESSAGE $display("\nDEBUG in %m @ tick %8d ", `U_TB.clk_count ); -`define TB_WARNING_MESSAGE $display("\nWARNING in %m @ tick %8d", `U_TB.clk_count ); -`define TB_ERROR_MESSAGE $display("\nFATAL ERROR in %m @ tick %8d", `U_TB.clk_count ); force `U_TB.testfail = 1'd1; - - -`ifdef XILINX_FPGA -// Full DDR3 memory Model -`define U_RAM tb.u_ddr3_model_c3.memory -`else -// Simplified Main Memory Model -`define U_RAM tb.u_system.u_main_mem.ram -`endif - -`endif diff --git a/cores/archie/bench/rtl/ioc_irq_tb.v b/cores/archie/bench/rtl/ioc_irq_tb.v deleted file mode 100644 index e7db38a..0000000 --- a/cores/archie/bench/rtl/ioc_irq_tb.v +++ /dev/null @@ -1,269 +0,0 @@ -`timescale 1ns / 1ps -/* ioc_irq_tb.v - - Copyright (c) 2012-2014, Stephen J. Leary - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -module ioc_irq_tb; - - // Inputs - reg CLK32M = 0; - reg CLK25M = 0; - - reg [31:0] ADDRESS = 0; - reg [7:0] DIN = 0; - wire[7:0] DOUT1,DOUT2,DOUT3; - - reg [7:0] I1 = 0; - reg [7:0] I2 = 0; - reg [7:0] I3 = 0; - - reg [7:0] C2 = 0; - reg [7:0] C3 = 0; - - wire IRQ1,IRQ2,IRQ3; - reg WR_RQ = 0; - - // Instantiate the Unit Under Test (UUT) - ioc_irq #( - .ADDRESS(2'b01), - .PERMBITS(8'h80) - ) UUT1 - ( - .clkcpu ( CLK32M ), - - .i ( I1 ), - .irq ( IRQ1 ), - - .addr ( {ADDRESS[6:2]}), - .din ( DIN ), - .dout ( DOUT1 ), - - .write ( WR_RQ ) - - ); - - // Instantiate the Unit Under Test (UUT) - ioc_irq #( - .ADDRESS(2'b10), - .CANCLEAR(1'b0) - ) UUT2 - ( - .clkcpu ( CLK32M ), - - .i ( I2 ), - .c ( C2 ), - .irq ( IRQ2 ), - - .addr ( ADDRESS[6:2]), - .din ( DIN ), - .dout ( DOUT2 ), - - .write ( WR_RQ ) - ); - - // Instantiate the Unit Under Test (UUT) - ioc_irq #( - .ADDRESS(2'b11), - .CANCLEAR(1'b0) - ) UUT3 - ( - .clkcpu ( CLK32M ), - - .i ( I3 ), - .c ( C3 ), - .irq ( IRQ3 ), - - .addr ( ADDRESS[6:2]), - .din ( DIN ), - .dout ( DOUT3 ), - - .write ( WR_RQ ) - ); - - initial begin - - $dumpfile("ioc_irq.vcd"); - $dumpvars(0, ioc_irq_tb); - - #500; - - wait(~CLK32M); - ADDRESS = 32'h03200010; - - wait(CLK32M); - wait(~CLK32M); - - if(!(DOUT1==8'h80)) begin $display("fail."); $finish; end - - wait(CLK32M); - wait(~CLK32M); - - I1 = 8'h42; - - wait(CLK32M); - wait(~CLK32M); - - I1 = 8'h00; - - wait(CLK32M); - wait(~CLK32M); - - if(!(DOUT1==8'hC2)) begin $display("fail."); $finish; end - - wait(CLK32M); - wait(~CLK32M); - - WR_RQ = 1; - ADDRESS = 32'h03200014; - DIN = 8'h40; - - wait(CLK32M); - wait(~CLK32M); - - ADDRESS = 32'h03200010; - WR_RQ = 0; - I1 = 8'h00; - - $display("address: %b", ADDRESS[6:2]); - - wait(CLK32M); - wait(~CLK32M); - - if(!(DOUT1==8'h82)) begin $display("fail."); $finish; end - if(IRQ1) begin $display("fail."); $finish; end - if(IRQ2) begin $display("fail."); $finish; end - if(IRQ3) begin $display("fail."); $finish; end - - ADDRESS = 32'h03200018; - WR_RQ = 1; - DIN = 8'h40; - - wait(CLK32M); - wait(~CLK32M); - - WR_RQ = 0; - if(IRQ1) begin $display("fail."); $finish; end - - wait(CLK32M); - wait(~CLK32M); - - if(IRQ1) begin $display("fail."); $finish; end - - wait(CLK32M); - wait(~CLK32M); - - if(IRQ1) begin $display("fail."); $finish; end - - I1 = 8'hFF; - - wait(CLK32M); - wait(~CLK32M); - - wait(CLK32M); - wait(~CLK32M); - - if(~IRQ1) begin $display("fail."); $finish; end - if(IRQ2) begin $display("fail."); $finish; end - if(IRQ3) begin $display("fail."); $finish; end - I1 = 8'h00; - - ADDRESS = 32'h03200014; - - wait(CLK32M); - wait(~CLK32M); - - if(!(DOUT1==8'h40)) begin $display("fail."); $finish; end - - wait(CLK32M); - wait(~CLK32M); - - ADDRESS = 32'h03200014; - WR_RQ = 1; - DIN = 8'h40; - - wait(CLK32M); - wait(~CLK32M); - - WR_RQ = 0; - if(IRQ1) begin $display("fail."); $finish; end - if(IRQ2) begin $display("fail."); $finish; end - if(IRQ3) begin $display("fail."); $finish; end - - // ok now test irq 2 - - ADDRESS = 32'h03200020; - - wait(CLK32M); - wait(~CLK32M); - - if(!(DOUT2==8'h00)) begin $display("fail."); $finish; end - - I2 = 8'h08; - - wait(CLK32M); - wait(~CLK32M); - - if(!(DOUT2==8'h08)) begin $display("fail."); $finish; end - - I2 = 8'h00; - - ADDRESS = 32'h03200024; - WR_RQ = 1; - DIN = 8'h08; - - wait(CLK32M); - wait(~CLK32M); - - WR_RQ = 0; - ADDRESS = 32'h03200020; - - wait(CLK32M); - wait(~CLK32M); - - // verify that the clear address doesnt work for these irq sources. - if(!(DOUT2==8'h08)) begin $display("fail."); $finish; end - - C2 = 8'h48; - - wait(CLK32M); - wait(~CLK32M); - - // verify that the clear address doesnt work for these irq sources. - if(!(DOUT2==8'h08)) begin $display("fail."); $finish; end - - #500; - $finish; - - - end - - always begin - #15; CLK32M = ~CLK32M; - end - -endmodule - diff --git a/cores/archie/bench/rtl/memc_translator_tb.v b/cores/archie/bench/rtl/memc_translator_tb.v deleted file mode 100644 index 172a735..0000000 --- a/cores/archie/bench/rtl/memc_translator_tb.v +++ /dev/null @@ -1,926 +0,0 @@ -`timescale 1ns / 1ps -/* memc_translator_tb.v - - Copyright (c) 2012-2014, Stephen J. Leary - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -module memc_translator_tb; - -// Inputs -reg CLK32M = 0; -reg CLK25M = 0; -reg MEMCTW = 0; -reg SPVMD = 0; -reg OSMD = 0; -reg MEMWE = 1; - -reg [25:0] addr_i; -wire [25:0] addr_o; -wire valid; - -// Instantiate the Unit Under Test (UUT) -memc_translator UUT ( - .clkcpu ( CLK32M ), - .wr ( MEMCTW ), - .mem_write ( MEMWE ), - .spvmd ( SPVMD ), - .osmd ( OSMD ), - .addr_i ( addr_i ), - .addr_o ( addr_o ), - .valid ( valid ) -); - - -task CHECK; -input expected; -input actual; -begin - if (expected != actual) begin - $display("Error: expected %b, actual %b", expected, actual); - $finish_and_return(-1); - end -end -endtask - -task SetMEMC; -input [31:0] address; -begin - MEMCTW <= 1; - SPVMD <= 1; - addr_i <= address; - #30; - MEMCTW <= 0; - #30; -end -endtask - -task CheckSPVMD; -input [31:0] address; -input expected; -begin - MEMCTW <= 0; - SPVMD <= 1; - addr_i <= address; - #30; - $display("Checking address %08x in Supervisor Mode: Valid = %b, Result = %08x", addr_i, valid, addr_o); - CHECK(expected, valid); - MEMCTW <= 0; - #30; -end -endtask - -task CheckOSMD; -input [31:0] address; -input expected; -begin - MEMCTW <= 0; - SPVMD <= 0; - OSMD <= 1; - addr_i <= address; - #30; - $display("Checking address %08x in OS Mode: Valid = %b, Result = %08x", addr_i, valid, addr_o); - CHECK(expected, valid); - MEMCTW <= 0; - #30; -end -endtask - -task CheckUser; -input [31:0] address; -input expected; -begin - MEMCTW <= 0; - SPVMD <= 0; - OSMD <= 0; - addr_i <= address; - #30; - $display("Checking address %08x in User Mode: Valid = %b, Result = %08x", addr_i, valid, addr_o); - CHECK(expected, valid); - MEMCTW <= 0; - #30; -end -endtask - - -initial begin - - $dumpfile("memc_translator.vcd"); - $dumpvars(0, UUT); - //$monitor ("%g %b %x %x", $time, CLK32M, MEMCTW, addr_i, addr_o); - - // Initialize Inputs - CLK32M = 0; - MEMCTW = 0; - SPVMD = 0; - - #30; - - $display("BangCam: R2 = 0x0000007f, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f7f); - - $display("BangCam: R2 = 0x0000007e, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f77); - - $display("BangCam: R2 = 0x0000007d, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f6f); - - $display("BangCam: R2 = 0x0000007c, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f67); - - $display("BangCam: R2 = 0x0000007b, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f5f); - - $display("BangCam: R2 = 0x0000007a, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f57); - - $display("BangCam: R2 = 0x00000079, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f4f); - - $display("BangCam: R2 = 0x00000078, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f47); - - $display("BangCam: R2 = 0x00000077, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f3f); - - $display("BangCam: R2 = 0x00000076, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f37); - - $display("BangCam: R2 = 0x00000075, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f2f); - - $display("BangCam: R2 = 0x00000074, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f27); - - $display("BangCam: R2 = 0x00000073, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f1f); - - $display("BangCam: R2 = 0x00000072, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f17); - - $display("BangCam: R2 = 0x00000071, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f0f); - - $display("BangCam: R2 = 0x00000070, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f07); - - $display("BangCam: R2 = 0x0000006f, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f7e); - - $display("BangCam: R2 = 0x0000006e, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f76); - - $display("BangCam: R2 = 0x0000006d, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f6e); - - $display("BangCam: R2 = 0x0000006c, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f66); - - $display("BangCam: R2 = 0x0000006b, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f5e); - - $display("BangCam: R2 = 0x0000006a, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f56); - - $display("BangCam: R2 = 0x00000069, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f4e); - - $display("BangCam: R2 = 0x00000068, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f46); - - $display("BangCam: R2 = 0x00000067, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f3e); - - $display("BangCam: R2 = 0x00000066, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f36); - - $display("BangCam: R2 = 0x00000065, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f2e); - - $display("BangCam: R2 = 0x00000064, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f26); - - $display("BangCam: R2 = 0x00000063, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f1e); - - $display("BangCam: R2 = 0x00000062, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f16); - - $display("BangCam: R2 = 0x00000061, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f0e); - - $display("BangCam: R2 = 0x00000060, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f06); - - $display("BangCam: R2 = 0x0000005f, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f7b); - - $display("BangCam: R2 = 0x0000005e, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f73); - - $display("BangCam: R2 = 0x0000005d, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f6b); - - $display("BangCam: R2 = 0x0000005c, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f63); - - $display("BangCam: R2 = 0x0000005b, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f5b); - - $display("BangCam: R2 = 0x0000005a, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f53); - - $display("BangCam: R2 = 0x00000059, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f4b); - - $display("BangCam: R2 = 0x00000058, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f43); - - $display("BangCam: R2 = 0x00000057, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f3b); - - $display("BangCam: R2 = 0x00000056, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f33); - - $display("BangCam: R2 = 0x00000055, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f2b); - - $display("BangCam: R2 = 0x00000054, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f23); - - $display("BangCam: R2 = 0x00000053, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f1b); - - $display("BangCam: R2 = 0x00000052, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f13); - - $display("BangCam: R2 = 0x00000051, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f0b); - - $display("BangCam: R2 = 0x00000050, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f03); - - $display("BangCam: R2 = 0x0000004f, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f7a); - - $display("BangCam: R2 = 0x0000004e, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f72); - - $display("BangCam: R2 = 0x0000004d, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f6a); - - $display("BangCam: R2 = 0x0000004c, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f62); - - $display("BangCam: R2 = 0x0000004b, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f5a); - - $display("BangCam: R2 = 0x0000004a, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f52); - - $display("BangCam: R2 = 0x00000049, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f4a); - - $display("BangCam: R2 = 0x00000048, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f42); - - $display("BangCam: R2 = 0x00000047, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f3a); - - $display("BangCam: R2 = 0x00000046, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f32); - - $display("BangCam: R2 = 0x00000045, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f2a); - - $display("BangCam: R2 = 0x00000044, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f22); - - $display("BangCam: R2 = 0x00000043, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f1a); - - $display("BangCam: R2 = 0x00000042, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f12); - - $display("BangCam: R2 = 0x00000041, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f0a); - - $display("BangCam: R2 = 0x00000040, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f02); - - $display("BangCam: R2 = 0x0000003f, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f7d); - - $display("BangCam: R2 = 0x0000003e, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f75); - - $display("BangCam: R2 = 0x0000003d, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f6d); - - $display("BangCam: R2 = 0x0000003c, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f65); - - $display("BangCam: R2 = 0x0000003b, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f5d); - - $display("BangCam: R2 = 0x0000003a, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f55); - - $display("BangCam: R2 = 0x00000039, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f4d); - - $display("BangCam: R2 = 0x00000038, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f45); - - $display("BangCam: R2 = 0x00000037, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f3d); - - $display("BangCam: R2 = 0x00000036, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f35); - - $display("BangCam: R2 = 0x00000035, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f2d); - - $display("BangCam: R2 = 0x00000034, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f25); - - $display("BangCam: R2 = 0x00000033, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f1d); - - $display("BangCam: R2 = 0x00000032, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f15); - - $display("BangCam: R2 = 0x00000031, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f0d); - - $display("BangCam: R2 = 0x00000030, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f05); - - $display("BangCam: R2 = 0x0000002f, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f7c); - - $display("BangCam: R2 = 0x0000002e, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f74); - - $display("BangCam: R2 = 0x0000002d, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f6c); - - $display("BangCam: R2 = 0x0000002c, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f64); - - $display("BangCam: R2 = 0x0000002b, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f5c); - - $display("BangCam: R2 = 0x0000002a, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f54); - - $display("BangCam: R2 = 0x00000029, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f4c); - - $display("BangCam: R2 = 0x00000028, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f44); - - $display("BangCam: R2 = 0x00000027, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f3c); - - $display("BangCam: R2 = 0x00000026, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f34); - - $display("BangCam: R2 = 0x00000025, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f2c); - - $display("BangCam: R2 = 0x00000024, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f24); - - $display("BangCam: R2 = 0x00000023, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f1c); - - $display("BangCam: R2 = 0x00000022, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f14); - - $display("BangCam: R2 = 0x00000021, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f0c); - - $display("BangCam: R2 = 0x00000020, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f04); - - $display("BangCam: R2 = 0x0000001f, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f79); - - $display("BangCam: R2 = 0x0000001e, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f71); - - $display("BangCam: R2 = 0x0000001d, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f69); - - $display("BangCam: R2 = 0x0000001c, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f61); - - $display("BangCam: R2 = 0x0000001b, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f59); - - $display("BangCam: R2 = 0x0000001a, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f51); - - $display("BangCam: R2 = 0x00000019, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f49); - - $display("BangCam: R2 = 0x00000018, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f41); - - $display("BangCam: R2 = 0x00000017, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f39); - - $display("BangCam: R2 = 0x00000016, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f31); - - $display("BangCam: R2 = 0x00000015, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f29); - - $display("BangCam: R2 = 0x00000014, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f21); - - $display("BangCam: R2 = 0x00000013, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f19); - - $display("BangCam: R2 = 0x00000012, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f11); - - $display("BangCam: R2 = 0x00000011, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f09); - - $display("BangCam: R2 = 0x00000010, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f01); - - $display("BangCam: R2 = 0x0000000f, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f78); - - $display("BangCam: R2 = 0x0000000e, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f70); - - $display("BangCam: R2 = 0x0000000d, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f68); - - $display("BangCam: R2 = 0x0000000c, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f60); - - $display("BangCam: R2 = 0x0000000b, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f58); - - $display("BangCam: R2 = 0x0000000a, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f50); - - $display("BangCam: R2 = 0x00000009, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f48); - - $display("BangCam: R2 = 0x00000008, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f40); - - $display("BangCam: R2 = 0x00000007, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f38); - - $display("BangCam: R2 = 0x00000006, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f30); - - $display("BangCam: R2 = 0x00000005, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f28); - - $display("BangCam: R2 = 0x00000004, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f20); - - $display("BangCam: R2 = 0x00000003, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f18); - - $display("BangCam: R2 = 0x00000002, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f10); - - $display("BangCam: R2 = 0x00000001, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f08); - - $display("BangCam: R2 = 0x00000000, R3 = 0x01f08000, R11 = 0x00000003"); - SetMEMC(32'h03f08f00); - - $display("BangCam: R2 = 0x0000000f, R3 = 0x01f00000, R11 = 0x00000001"); - SetMEMC(32'h03f00d78); - - $display("BangCam: R2 = 0x00000011, R3 = 0x01c00000, R11 = 0x00000000"); - SetMEMC(32'h03c00c09); - - $display("BangCam: R2 = 0x00000010, R3 = 0x00000000, R11 = 0x00000000"); - SetMEMC(32'h03800001); - - $display("BangCam: R2 = 0x00000000, R3 = 0x01fb0000, R11 = 0x00000000"); - SetMEMC(32'h03fb0c00); - - $display("BangCam: R2 = 0x00000001, R3 = 0x01fb8000, R11 = 0x00000000"); - SetMEMC(32'h03fb8c08); - - $display("BangCam: R2 = 0x00000002, R3 = 0x01fc0000, R11 = 0x00000000"); - SetMEMC(32'h03fc0c10); - - $display("BangCam: R2 = 0x00000003, R3 = 0x01fc8000, R11 = 0x00000000"); - SetMEMC(32'h03fc8c18); - - $display("BangCam: R2 = 0x00000004, R3 = 0x01fd0000, R11 = 0x00000000"); - SetMEMC(32'h03fd0c20); - - $display("BangCam: R2 = 0x00000005, R3 = 0x01fd8000, R11 = 0x00000000"); - SetMEMC(32'h03fd8c28); - - $display("BangCam: R2 = 0x00000006, R3 = 0x01fe0000, R11 = 0x00000000"); - SetMEMC(32'h03fe0c30); - - $display("BangCam: R2 = 0x00000007, R3 = 0x01fe8000, R11 = 0x00000000"); - SetMEMC(32'h03fe8c38); - - $display("BangCam: R2 = 0x00000008, R3 = 0x01ff0000, R11 = 0x00000000"); - SetMEMC(32'h03ff0c40); - - $display("BangCam: R2 = 0x00000009, R3 = 0x01ff8000, R11 = 0x00000000"); - SetMEMC(32'h03ff8c48); - - $display("BangCam: R2 = 0x0000000a, R3 = 0x01800000, R11 = 0x00000000"); - SetMEMC(32'h03800c50); - - $display("BangCam: R2 = 0x0000000b, R3 = 0x01e00000, R11 = 0x00000002"); - SetMEMC(32'h03e00e58); - - $display("BangCam: R2 = 0x0000000c, R3 = 0x01e08000, R11 = 0x00000002"); - SetMEMC(32'h03e08e60); - - $display("BangCam: R2 = 0x0000000d, R3 = 0x01e10000, R11 = 0x00000002"); - SetMEMC(32'h03e10e68); - - $display("BangCam: R2 = 0x0000000e, R3 = 0x01e18000, R11 = 0x00000002"); - SetMEMC(32'h03e18e70); - - $display("BangCam: R2 = 0x00000012, R3 = 0x00008000, R11 = 0x00000000"); - SetMEMC(32'h03808011); - - $display("BangCam: R2 = 0x00000013, R3 = 0x00010000, R11 = 0x00000000"); - SetMEMC(32'h03810019); - - $display("BangCam: R2 = 0x00000014, R3 = 0x00018000, R11 = 0x00000000"); - SetMEMC(32'h03818021); - - $display("BangCam: R2 = 0x00000015, R3 = 0x00020000, R11 = 0x00000000"); - SetMEMC(32'h03820029); - - $display("BangCam: R2 = 0x00000016, R3 = 0x00028000, R11 = 0x00000000"); - SetMEMC(32'h03828031); - - $display("BangCam: R2 = 0x00000017, R3 = 0x00030000, R11 = 0x00000000"); - SetMEMC(32'h03830039); - - $display("BangCam: R2 = 0x00000018, R3 = 0x00038000, R11 = 0x00000000"); - SetMEMC(32'h03838041); - - $display("BangCam: R2 = 0x00000019, R3 = 0x00040000, R11 = 0x00000000"); - SetMEMC(32'h03840049); - - $display("BangCam: R2 = 0x0000001a, R3 = 0x00048000, R11 = 0x00000000"); - SetMEMC(32'h03848051); - - $display("BangCam: R2 = 0x0000001b, R3 = 0x00050000, R11 = 0x00000000"); - SetMEMC(32'h03850059); - - $display("BangCam: R2 = 0x0000001c, R3 = 0x00058000, R11 = 0x00000000"); - SetMEMC(32'h03858061); - - $display("BangCam: R2 = 0x0000001d, R3 = 0x00060000, R11 = 0x00000000"); - SetMEMC(32'h03860069); - - $display("BangCam: R2 = 0x0000001e, R3 = 0x00068000, R11 = 0x00000000"); - SetMEMC(32'h03868071); - - $display("BangCam: R2 = 0x0000001f, R3 = 0x00070000, R11 = 0x00000000"); - SetMEMC(32'h03870079); - - $display("BangCam: R2 = 0x00000020, R3 = 0x00078000, R11 = 0x00000000"); - SetMEMC(32'h03878004); - - $display("BangCam: R2 = 0x00000021, R3 = 0x00080000, R11 = 0x00000000"); - SetMEMC(32'h0388000c); - - $display("BangCam: R2 = 0x00000022, R3 = 0x00088000, R11 = 0x00000000"); - SetMEMC(32'h03888014); - - $display("BangCam: R2 = 0x00000023, R3 = 0x00090000, R11 = 0x00000000"); - SetMEMC(32'h0389001c); - - $display("BangCam: R2 = 0x00000024, R3 = 0x00098000, R11 = 0x00000000"); - SetMEMC(32'h03898024); - - $display("BangCam: R2 = 0x00000025, R3 = 0x000a0000, R11 = 0x00000000"); - SetMEMC(32'h038a002c); - - $display("BangCam: R2 = 0x00000026, R3 = 0x000a8000, R11 = 0x00000000"); - SetMEMC(32'h038a8034); - - $display("BangCam: R2 = 0x00000027, R3 = 0x000b0000, R11 = 0x00000000"); - SetMEMC(32'h038b003c); - - $display("BangCam: R2 = 0x00000028, R3 = 0x000b8000, R11 = 0x00000000"); - SetMEMC(32'h038b8044); - - $display("BangCam: R2 = 0x00000029, R3 = 0x000c0000, R11 = 0x00000000"); - SetMEMC(32'h038c004c); - - $display("BangCam: R2 = 0x0000002a, R3 = 0x000c8000, R11 = 0x00000000"); - SetMEMC(32'h038c8054); - - $display("BangCam: R2 = 0x0000002b, R3 = 0x000d0000, R11 = 0x00000000"); - SetMEMC(32'h038d005c); - - $display("BangCam: R2 = 0x0000002c, R3 = 0x000d8000, R11 = 0x00000000"); - SetMEMC(32'h038d8064); - - $display("BangCam: R2 = 0x0000002d, R3 = 0x000e0000, R11 = 0x00000000"); - SetMEMC(32'h038e006c); - - $display("BangCam: R2 = 0x0000002e, R3 = 0x000e8000, R11 = 0x00000000"); - SetMEMC(32'h038e8074); - - $display("BangCam: R2 = 0x0000002f, R3 = 0x000f0000, R11 = 0x00000000"); - SetMEMC(32'h038f007c); - - $display("BangCam: R2 = 0x00000030, R3 = 0x000f8000, R11 = 0x00000000"); - SetMEMC(32'h038f8005); - - $display("BangCam: R2 = 0x00000031, R3 = 0x00100000, R11 = 0x00000000"); - SetMEMC(32'h0390000d); - - $display("BangCam: R2 = 0x00000032, R3 = 0x00108000, R11 = 0x00000000"); - SetMEMC(32'h03908015); - - $display("BangCam: R2 = 0x00000033, R3 = 0x00110000, R11 = 0x00000000"); - SetMEMC(32'h0391001d); - - $display("BangCam: R2 = 0x00000034, R3 = 0x00118000, R11 = 0x00000000"); - SetMEMC(32'h03918025); - - $display("BangCam: R2 = 0x00000035, R3 = 0x00120000, R11 = 0x00000000"); - SetMEMC(32'h0392002d); - - $display("BangCam: R2 = 0x00000036, R3 = 0x00128000, R11 = 0x00000000"); - SetMEMC(32'h03928035); - - $display("BangCam: R2 = 0x00000037, R3 = 0x00130000, R11 = 0x00000000"); - SetMEMC(32'h0393003d); - - $display("BangCam: R2 = 0x00000038, R3 = 0x00138000, R11 = 0x00000000"); - SetMEMC(32'h03938045); - - $display("BangCam: R2 = 0x00000039, R3 = 0x00140000, R11 = 0x00000000"); - SetMEMC(32'h0394004d); - - $display("BangCam: R2 = 0x0000003a, R3 = 0x00148000, R11 = 0x00000000"); - SetMEMC(32'h03948055); - - $display("BangCam: R2 = 0x0000003b, R3 = 0x00150000, R11 = 0x00000000"); - SetMEMC(32'h0395005d); - - $display("BangCam: R2 = 0x0000003c, R3 = 0x00158000, R11 = 0x00000000"); - SetMEMC(32'h03958065); - - $display("BangCam: R2 = 0x0000003d, R3 = 0x00160000, R11 = 0x00000000"); - SetMEMC(32'h0396006d); - - $display("BangCam: R2 = 0x0000003e, R3 = 0x00168000, R11 = 0x00000000"); - SetMEMC(32'h03968075); - - $display("BangCam: R2 = 0x0000003f, R3 = 0x00170000, R11 = 0x00000000"); - SetMEMC(32'h0397007d); - - $display("BangCam: R2 = 0x00000040, R3 = 0x00178000, R11 = 0x00000000"); - SetMEMC(32'h03978002); - - $display("BangCam: R2 = 0x00000041, R3 = 0x00180000, R11 = 0x00000000"); - SetMEMC(32'h0398000a); - - $display("BangCam: R2 = 0x00000042, R3 = 0x00188000, R11 = 0x00000000"); - SetMEMC(32'h03988012); - - $display("BangCam: R2 = 0x00000043, R3 = 0x00190000, R11 = 0x00000000"); - SetMEMC(32'h0399001a); - - $display("BangCam: R2 = 0x00000044, R3 = 0x00198000, R11 = 0x00000000"); - SetMEMC(32'h03998022); - - $display("BangCam: R2 = 0x00000045, R3 = 0x001a0000, R11 = 0x00000000"); - SetMEMC(32'h039a002a); - - $display("BangCam: R2 = 0x00000046, R3 = 0x001a8000, R11 = 0x00000000"); - SetMEMC(32'h039a8032); - - $display("BangCam: R2 = 0x00000047, R3 = 0x001b0000, R11 = 0x00000000"); - SetMEMC(32'h039b003a); - - $display("BangCam: R2 = 0x00000048, R3 = 0x001b8000, R11 = 0x00000000"); - SetMEMC(32'h039b8042); - - $display("BangCam: R2 = 0x00000049, R3 = 0x001c0000, R11 = 0x00000000"); - SetMEMC(32'h039c004a); - - $display("BangCam: R2 = 0x0000004a, R3 = 0x001c8000, R11 = 0x00000000"); - SetMEMC(32'h039c8052); - - $display("BangCam: R2 = 0x0000004b, R3 = 0x001d0000, R11 = 0x00000000"); - SetMEMC(32'h039d005a); - - $display("BangCam: R2 = 0x0000004c, R3 = 0x001d8000, R11 = 0x00000000"); - SetMEMC(32'h039d8062); - - $display("BangCam: R2 = 0x0000004d, R3 = 0x001e0000, R11 = 0x00000000"); - SetMEMC(32'h039e006a); - - $display("BangCam: R2 = 0x0000004e, R3 = 0x001e8000, R11 = 0x00000000"); - SetMEMC(32'h039e8072); - - $display("BangCam: R2 = 0x0000004f, R3 = 0x001f0000, R11 = 0x00000000"); - SetMEMC(32'h039f007a); - - $display("BangCam: R2 = 0x00000050, R3 = 0x001f8000, R11 = 0x00000000"); - SetMEMC(32'h039f8003); - - $display("BangCam: R2 = 0x00000051, R3 = 0x00200000, R11 = 0x00000000"); - SetMEMC(32'h03a0000b); - - $display("BangCam: R2 = 0x00000052, R3 = 0x00208000, R11 = 0x00000000"); - SetMEMC(32'h03a08013); - - $display("BangCam: R2 = 0x00000053, R3 = 0x00210000, R11 = 0x00000000"); - SetMEMC(32'h03a1001b); - - $display("BangCam: R2 = 0x00000054, R3 = 0x00218000, R11 = 0x00000000"); - SetMEMC(32'h03a18023); - - $display("BangCam: R2 = 0x00000055, R3 = 0x00220000, R11 = 0x00000000"); - SetMEMC(32'h03a2002b); - - $display("BangCam: R2 = 0x00000056, R3 = 0x00228000, R11 = 0x00000000"); - SetMEMC(32'h03a28033); - - $display("BangCam: R2 = 0x00000057, R3 = 0x00230000, R11 = 0x00000000"); - SetMEMC(32'h03a3003b); - - $display("BangCam: R2 = 0x00000058, R3 = 0x00238000, R11 = 0x00000000"); - SetMEMC(32'h03a38043); - - $display("BangCam: R2 = 0x00000059, R3 = 0x00240000, R11 = 0x00000000"); - SetMEMC(32'h03a4004b); - - $display("BangCam: R2 = 0x0000005a, R3 = 0x00248000, R11 = 0x00000000"); - SetMEMC(32'h03a48053); - - $display("BangCam: R2 = 0x0000005b, R3 = 0x00250000, R11 = 0x00000000"); - SetMEMC(32'h03a5005b); - - $display("BangCam: R2 = 0x0000005c, R3 = 0x00258000, R11 = 0x00000000"); - SetMEMC(32'h03a58063); - - $display("BangCam: R2 = 0x0000005d, R3 = 0x00260000, R11 = 0x00000000"); - SetMEMC(32'h03a6006b); - - $display("BangCam: R2 = 0x0000005e, R3 = 0x00268000, R11 = 0x00000000"); - SetMEMC(32'h03a68073); - - $display("BangCam: R2 = 0x0000005f, R3 = 0x00270000, R11 = 0x00000000"); - SetMEMC(32'h03a7007b); - - $display("BangCam: R2 = 0x00000060, R3 = 0x00278000, R11 = 0x00000000"); - SetMEMC(32'h03a78006); - - $display("BangCam: R2 = 0x00000061, R3 = 0x00280000, R11 = 0x00000000"); - SetMEMC(32'h03a8000e); - - $display("BangCam: R2 = 0x00000062, R3 = 0x00288000, R11 = 0x00000000"); - SetMEMC(32'h03a88016); - - $display("BangCam: R2 = 0x00000063, R3 = 0x00290000, R11 = 0x00000000"); - SetMEMC(32'h03a9001e); - - $display("BangCam: R2 = 0x00000064, R3 = 0x00298000, R11 = 0x00000000"); - SetMEMC(32'h03a98026); - - $display("BangCam: R2 = 0x00000065, R3 = 0x002a0000, R11 = 0x00000000"); - SetMEMC(32'h03aa002e); - - $display("BangCam: R2 = 0x00000066, R3 = 0x002a8000, R11 = 0x00000000"); - SetMEMC(32'h03aa8036); - - $display("BangCam: R2 = 0x00000067, R3 = 0x002b0000, R11 = 0x00000000"); - SetMEMC(32'h03ab003e); - - $display("BangCam: R2 = 0x00000068, R3 = 0x002b8000, R11 = 0x00000000"); - SetMEMC(32'h03ab8046); - - $display("BangCam: R2 = 0x00000069, R3 = 0x002c0000, R11 = 0x00000000"); - SetMEMC(32'h03ac004e); - - $display("BangCam: R2 = 0x0000006a, R3 = 0x002c8000, R11 = 0x00000000"); - SetMEMC(32'h03ac8056); - - $display("BangCam: R2 = 0x0000006b, R3 = 0x002d0000, R11 = 0x00000000"); - SetMEMC(32'h03ad005e); - - $display("BangCam: R2 = 0x0000006c, R3 = 0x002d8000, R11 = 0x00000000"); - SetMEMC(32'h03ad8066); - - $display("BangCam: R2 = 0x0000006d, R3 = 0x002e0000, R11 = 0x00000000"); - SetMEMC(32'h03ae006e); - - $display("BangCam: R2 = 0x0000006e, R3 = 0x002e8000, R11 = 0x00000000"); - SetMEMC(32'h03ae8076); - - $display("BangCam: R2 = 0x0000006f, R3 = 0x002f0000, R11 = 0x00000000"); - SetMEMC(32'h03af007e); - - $display("BangCam: R2 = 0x00000070, R3 = 0x002f8000, R11 = 0x00000000"); - SetMEMC(32'h03af8007); - - $display("BangCam: R2 = 0x00000071, R3 = 0x00300000, R11 = 0x00000000"); - SetMEMC(32'h03b0000f); - - $display("BangCam: R2 = 0x00000072, R3 = 0x00308000, R11 = 0x00000000"); - SetMEMC(32'h03b08017); - - $display("BangCam: R2 = 0x00000073, R3 = 0x00310000, R11 = 0x00000000"); - SetMEMC(32'h03b1001f); - - $display("BangCam: R2 = 0x00000074, R3 = 0x00318000, R11 = 0x00000000"); - SetMEMC(32'h03b18027); - - $display("BangCam: R2 = 0x00000075, R3 = 0x00320000, R11 = 0x00000000"); - SetMEMC(32'h03b2002f); - - $display("BangCam: R2 = 0x00000076, R3 = 0x00328000, R11 = 0x00000000"); - SetMEMC(32'h03b28037); - - $display("BangCam: R2 = 0x00000077, R3 = 0x00330000, R11 = 0x00000000"); - SetMEMC(32'h03b3003f); - - $display("BangCam: R2 = 0x00000078, R3 = 0x00338000, R11 = 0x00000000"); - SetMEMC(32'h03b38047); - - $display("BangCam: R2 = 0x00000079, R3 = 0x00340000, R11 = 0x00000000"); - SetMEMC(32'h03b4004f); - - $display("BangCam: R2 = 0x0000007a, R3 = 0x00348000, R11 = 0x00000000"); - SetMEMC(32'h03b48057); - - $display("BangCam: R2 = 0x0000007b, R3 = 0x00350000, R11 = 0x00000000"); - SetMEMC(32'h03b5005f); - - $display("BangCam: R2 = 0x0000007c, R3 = 0x00358000, R11 = 0x00000000"); - SetMEMC(32'h03b58067); - - $display("BangCam: R2 = 0x0000007d, R3 = 0x00360000, R11 = 0x00000000"); - SetMEMC(32'h03b6006f); - - $display("BangCam: R2 = 0x0000007e, R3 = 0x00368000, R11 = 0x00000000"); - SetMEMC(32'h03b68077); - - $display("BangCam: R2 = 0x0000007f, R3 = 0x00370000, R11 = 0x00000000"); - SetMEMC(32'h03b7007f); - - CheckSPVMD(32'h01F01350, 1); - - CheckOSMD(32'h01F01350, 0); - - CheckUser(32'h01F01350, 0); - - - #60; - $finish(); - - end - - always begin - #15; CLK32M = ~CLK32M; - end - -endmodule - diff --git a/cores/archie/bench/rtl/mt48lc16m16a2.v b/cores/archie/bench/rtl/mt48lc16m16a2.v deleted file mode 100644 index a8f101e..0000000 --- a/cores/archie/bench/rtl/mt48lc16m16a2.v +++ /dev/null @@ -1,1246 +0,0 @@ -`timescale 1ns/10ps -/************************************************************************** -* -* File Name: MT48LC16M16A2.V -* Version: 2.1 -* Date: June 6th, 2002 -* Model: BUS Functional -* Simulator: Model Technology -* -* Dependencies: None -* -* Email: modelsupport@micron.com -* Company: Micron Technology, Inc. -* Model: MT48LC16M16A2 (4Meg x 16 x 4 Banks) -* -* Description: Micron 256Mb SDRAM Verilog model -* -* Limitation: - Doesn't check for 8192 cycle refresh -* -* Note: - Set simulator resolution to "ps" accuracy -* - Set Debug = 0 to disable $display messages -* -* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY -* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY -* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR -* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. -* -* Copyright © 2001 Micron Semiconductor Products, Inc. -* All rights researved -* -* Rev Author Date Changes -* --- -------------------------- --------------------------------------- -* 2.1 SH 06/06/2002 - Typo in bank multiplex -* Micron Technology Inc. -* -* 2.0 SH 04/30/2002 - Second release -* Micron Technology Inc. -* -**************************************************************************/ - -// Uncomment one of the following to have the appropriate size definitions -// for the part. -//`define MT48LC32M16 // 64MB part -`define MT48LC16M16 // 32MB part -`define PRELOAD_RAM -//`define MT48LC4M16 // 8MB part - -module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm); - - -`ifdef MT48LC32M16 - // Params. for mt48lc32m16a2 (64MB part) - parameter addr_bits = 13; - parameter col_bits = 10; - parameter mem_sizes = 8388608; -`endif - -`ifdef MT48LC16M16 - // Params. for mt48lc16m16a2 (32MB part) - parameter addr_bits = 13; - parameter col_bits = 9; - parameter mem_sizes = 4194304; -`endif - -`ifdef MT48LC4M16 - //Params for mt48lc4m16a2 (8MB part) - parameter addr_bits = 12; - parameter col_bits = 8; - parameter mem_sizes = 1048576; -`endif - - // Common to all parts - parameter data_bits = 16; - - inout [data_bits - 1 : 0] Dq; - input [addr_bits - 1 : 0] Addr; - input [1 : 0] Ba; - input Clk; - input Cke; - input Cs_n; - input Ras_n; - input Cas_n; - input We_n; - input [1 : 0] Dqm; - - reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes]; - reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes]; - reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes]; - reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes]; - reg [31 : 0] Bank0_32bit [0 : (mem_sizes/2)]; // Temporary 32-bit wide array to hold readmemh()'d data before loading into 16-bit wide array - reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline - reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline - reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline - reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline - reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr; - - reg [addr_bits - 1 : 0] Mode_reg; - reg [data_bits - 1 : 0] Dq_reg, Dq_dqm; - reg [col_bits - 1 : 0] Col_temp, Burst_counter; - - reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate - reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge - - reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command - reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks) - reg Auto_precharge [0 : 3]; // RW Auto Precharge (Bank) - reg Read_precharge [0 : 3]; // R Auto Precharge - reg Write_precharge [0 : 3]; // W Auto Precharge - reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge - reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge - reg [1 : 0] RW_interrupt_bank; // RW Interrupt Bank - integer RW_interrupt_counter [0 : 3]; // RW Interrupt Counter - integer Count_precharge [0 : 3]; // RW Auto Precharge Counter - - reg Data_in_enable; - reg Data_out_enable; - - reg [1 : 0] Bank, Prev_bank; - reg [addr_bits - 1 : 0] Row; - reg [col_bits - 1 : 0] Col, Col_brst; - - // Internal system clock - reg CkeZ, Sys_clk; - - // Commands Decode - wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n; - wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n; - wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n; - wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n; - wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n; - wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n; - wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n; - - // Burst Length Decode - wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0]; - wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0]; - wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0]; - wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; - wire Burst_length_f = Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; - - // CAS Latency Decode - wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4]; - wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4]; - - // Write Burst Mode - wire Write_burst_mode = Mode_reg[9]; - - wire Debug = 1'b0; // Debug messages : 1 = On - wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ - - assign Dq = Dq_reg; // DQ buffer - - // Commands Operation - `define ACT 0 - `define NOP 1 - `define READ 2 - `define WRITE 3 - `define PRECH 4 - `define A_REF 5 - `define BST 6 - `define LMR 7 - - // Timing Parameters for -7E PC133 CL2 - parameter tAC = 5.4; - parameter tHZ = 5.4; - parameter tOH = 3.0; - parameter tMRD = 2.0; // 2 Clk Cycles - parameter tRAS = 37.0; - parameter tRC = 60.0; - parameter tRCD = 15.0; - parameter tRFC = 66.0; - parameter tRP = 15.0; - parameter tRRD = 14.0; - parameter tWRa = 7.0; // A2 Version - Auto precharge mode (1 Clk + 7 ns) - parameter tWRm = 14.0; // A2 Version - Manual precharge mode (14 ns) - - // Timing Check variable - time MRD_chk; - time WR_chkm [0 : 3]; - time RFC_chk, RRD_chk; - time RC_chk0, RC_chk1, RC_chk2, RC_chk3; - time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; - time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; - time RP_chk0, RP_chk1, RP_chk2, RP_chk3; - - integer mem_cnt; - - - initial begin - Dq_reg = {data_bits{1'bz}}; - Data_in_enable = 0; Data_out_enable = 0; - Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1; - Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0; - WR_chkm[0] = 0; WR_chkm[1] = 0; WR_chkm[2] = 0; WR_chkm[3] = 0; - RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0; - RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0; - MRD_chk = 0; RFC_chk = 0; RRD_chk = 0; - RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0; - RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0; - RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0; - RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0; - $timeformat (-9, 1, " ns", 12); -`ifdef INIT_CLEAR_MEM_BANKS // Added, jb - // Initialse the memory before we use it, clearing x's - for(mem_cnt = 0; mem_cnt < mem_sizes; mem_cnt = mem_cnt + 1) - begin - Bank0[mem_cnt] = 0; - Bank1[mem_cnt] = 0; - Bank2[mem_cnt] = 0; - Bank3[mem_cnt] = 0; - end -`endif - -`ifdef PRELOAD_RAM // Added jb - $display("* Preloading SDRAM bank 0.\n"); - // Uses the vmem file for the internal SRAM, so words are 32-bits wide - // and we need to copy them into the 16-bit wide array, which the simulator - // can't figure out how to do, so we'll do it manually here. - $readmemh("sram.vmem", Bank0_32bit); - for (mem_cnt=0;mem_cnt < (mem_sizes/2); mem_cnt = mem_cnt + 1) - begin - Bank0[(mem_cnt*2)+1] = Bank0_32bit[mem_cnt][15:0]; - Bank0[(mem_cnt*2)] = Bank0_32bit[mem_cnt][31:16]; - end -`endif -end - - // System clock generator - always begin - @ (posedge Clk) begin - Sys_clk = CkeZ; - CkeZ = Cke; - end - @ (negedge Clk) begin - Sys_clk = 1'b0; - end - end - - always @ (posedge Sys_clk) begin - // Internal Commamd Pipelined - Command[0] = Command[1]; - Command[1] = Command[2]; - Command[2] = Command[3]; - Command[3] = `NOP; - - Col_addr[0] = Col_addr[1]; - Col_addr[1] = Col_addr[2]; - Col_addr[2] = Col_addr[3]; - Col_addr[3] = {col_bits{1'b0}}; - - Bank_addr[0] = Bank_addr[1]; - Bank_addr[1] = Bank_addr[2]; - Bank_addr[2] = Bank_addr[3]; - Bank_addr[3] = 2'b0; - - Bank_precharge[0] = Bank_precharge[1]; - Bank_precharge[1] = Bank_precharge[2]; - Bank_precharge[2] = Bank_precharge[3]; - Bank_precharge[3] = 2'b0; - - A10_precharge[0] = A10_precharge[1]; - A10_precharge[1] = A10_precharge[2]; - A10_precharge[2] = A10_precharge[3]; - A10_precharge[3] = 1'b0; - - // Dqm pipeline for Read - Dqm_reg0 = Dqm_reg1; - Dqm_reg1 = Dqm; - - // Read or Write with Auto Precharge Counter - if (Auto_precharge[0] === 1'b1) begin - Count_precharge[0] = Count_precharge[0] + 1; - end - if (Auto_precharge[1] === 1'b1) begin - Count_precharge[1] = Count_precharge[1] + 1; - end - if (Auto_precharge[2] === 1'b1) begin - Count_precharge[2] = Count_precharge[2] + 1; - end - if (Auto_precharge[3] === 1'b1) begin - Count_precharge[3] = Count_precharge[3] + 1; - end - - // Read or Write Interrupt Counter - if (RW_interrupt_write[0] === 1'b1) begin - RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1; - end - if (RW_interrupt_write[1] === 1'b1) begin - RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1; - end - if (RW_interrupt_write[2] === 1'b1) begin - RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1; - end - if (RW_interrupt_write[3] === 1'b1) begin - RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1; - end - - // tMRD Counter - MRD_chk = MRD_chk + 1; - - // Auto Refresh - if (Aref_enable === 1'b1) begin - if (Debug) begin - $display ("%m : at time %t AREF : Auto Refresh", $time); - end - - // Auto Refresh to Auto Refresh - if ($time - RFC_chk < tRFC) begin - $display ("%m : at time %t ERROR: tRFC violation during Auto Refresh %t %t", $time, $time - RFC_chk, tRFC); - end - - // Precharge to Auto Refresh - if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || - ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin - $display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time); - end - - // Precharge to Refresh - if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin - $display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time); - end - - // Load Mode Register to Auto Refresh - if (MRD_chk < tMRD) begin - $display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time); - end - - // Record Current tRFC time - RFC_chk = $time; - end - - // Load Mode Register - if (Mode_reg_enable === 1'b1) begin - // Register Mode - Mode_reg = Addr; - - // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode - if (Debug) begin - $display ("%m : at time %t LMR : Load Mode Register", $time); - // CAS Latency - case (Addr[6 : 4]) - 3'b010 : $display ("%m : CAS Latency = 2"); - 3'b011 : $display ("%m : CAS Latency = 3"); - default : $display ("%m : CAS Latency = Reserved"); - endcase - - // Burst Length - case (Addr[2 : 0]) - 3'b000 : $display ("%m : Burst Length = 1"); - 3'b001 : $display ("%m : Burst Length = 2"); - 3'b010 : $display ("%m : Burst Length = 4"); - 3'b011 : $display ("%m : Burst Length = 8"); - 3'b111 : $display ("%m : Burst Length = Full"); - default : $display ("%m : Burst Length = Reserved"); - endcase - - // Burst Type - if (Addr[3] === 1'b0) begin - $display ("%m : Burst Type = Sequential"); - end else if (Addr[3] === 1'b1) begin - $display ("%m : Burst Type = Interleaved"); - end else begin - $display ("%m : Burst Type = Reserved"); - end - - // Write Burst Mode - if (Addr[9] === 1'b0) begin - $display ("%m : Write Burst Mode = Programmed Burst Length"); - end else if (Addr[9] === 1'b1) begin - $display ("%m : Write Burst Mode = Single Location Access"); - end else begin - $display ("%m : Write Burst Mode = Reserved"); - end - end - - // Precharge to Load Mode Register - if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin - $display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time); - end - - // Precharge to Load Mode Register - if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || - ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin - $display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time); - end - - // Auto Refresh to Load Mode Register - if ($time - RFC_chk < tRFC) begin - $display ("%m : at time %t ERROR: tRFC violation during Load Mode Register", $time); - end - - // Load Mode Register to Load Mode Register - if (MRD_chk < tMRD) begin - $display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time); - end - - // Reset MRD Counter - MRD_chk = 0; - end - - // Active Block (Latch Bank Address and Row Address) - if (Active_enable === 1'b1) begin - - // Activate an open bank can corrupt data - if ((Ba === 2'b00 && Act_b0 === 1'b1) || (Ba === 2'b01 && Act_b1 === 1'b1) || - (Ba === 2'b10 && Act_b2 === 1'b1) || (Ba === 2'b11 && Act_b3 === 1'b1)) begin - $display ("%m : at time %t ERROR: Bank already activated -- data can be corrupted", $time); - end - - // Activate Bank 0 - if (Ba === 2'b00 && Pc_b0 === 1'b1) begin - // Debug Message - if (Debug) begin - $display ("%m : at time %t ACT : Bank = 0 Row = %h", $time, Addr); - end - - // ACTIVE to ACTIVE command period - if ($time - RC_chk0 < tRC) begin - $display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time); - end - - // Precharge to Activate Bank 0 - if ($time - RP_chk0 < tRP) begin - $display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time); - end - - // Record variables - Act_b0 = 1'b1; - $display ("%m : Bank 0 activated at time %t", $time); - Pc_b0 = 1'b0; - B0_row_addr = Addr [addr_bits - 1 : 0]; - RAS_chk0 = $time; - RC_chk0 = $time; - RCD_chk0 = $time; - end - - if (Ba == 2'b01 && Pc_b1 == 1'b1) begin - // Debug Message - if (Debug) begin - $display ("%m : at time %t ACT : Bank = 1 Row = %h", $time, Addr); - end - - // ACTIVE to ACTIVE command period - if ($time - RC_chk1 < tRC) begin - $display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time); - end - - // Precharge to Activate Bank 1 - if ($time - RP_chk1 < tRP) begin - $display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time); - end - - // Record variables - Act_b1 = 1'b1; - Pc_b1 = 1'b0; - B1_row_addr = Addr [addr_bits - 1 : 0]; - RAS_chk1 = $time; - RC_chk1 = $time; - RCD_chk1 = $time; - end - - if (Ba == 2'b10 && Pc_b2 == 1'b1) begin - // Debug Message - if (Debug) begin - $display ("%m : at time %t ACT : Bank = 2 Row = %h", $time, Addr); - end - - // ACTIVE to ACTIVE command period - if ($time - RC_chk2 < tRC) begin - $display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time); - end - - // Precharge to Activate Bank 2 - if ($time - RP_chk2 < tRP) begin - $display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time); - end - - // Record variables - Act_b2 = 1'b1; - Pc_b2 = 1'b0; - B2_row_addr = Addr [addr_bits - 1 : 0]; - RAS_chk2 = $time; - RC_chk2 = $time; - RCD_chk2 = $time; - end - - if (Ba == 2'b11 && Pc_b3 == 1'b1) begin - // Debug Message - if (Debug) begin - $display ("%m : at time %t ACT : Bank = 3 Row = %h", $time, Addr); - end - - // ACTIVE to ACTIVE command period - if ($time - RC_chk3 < tRC) begin - $display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time); - end - - // Precharge to Activate Bank 3 - if ($time - RP_chk3 < tRP) begin - $display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time); - end - - // Record variables - Act_b3 = 1'b1; - Pc_b3 = 1'b0; - B3_row_addr = Addr [addr_bits - 1 : 0]; - RAS_chk3 = $time; - RC_chk3 = $time; - RCD_chk3 = $time; - end - - // Active Bank A to Active Bank B - if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin - $display ("%m : at time %t ERROR: tRRD violation during Activate bank = %h", $time, Ba); - end - - // Auto Refresh to Activate - if ($time - RFC_chk < tRFC) begin - $display ("%m : at time %t ERROR: tRFC violation during Activate bank = %h", $time, Ba); - end - - // Load Mode Register to Active - if (MRD_chk < tMRD ) begin - $display ("%m : at time %t ERROR: tMRD violation during Activate bank = %h", $time, Ba); - end - - // Record variables for checking violation - RRD_chk = $time; - Prev_bank = Ba; - end - - // Precharge Block - if (Prech_enable == 1'b1) begin - // Load Mode Register to Precharge - if ($time - MRD_chk < tMRD) begin - $display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time); - end - - - - // Precharge Bank 0 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin - Act_b0 = 1'b0; - Pc_b0 = 1'b1; - RP_chk0 = $time; - $display ("%m : Precharge bank 0 at time %t", $time); - // Activate to Precharge - if ($time - RAS_chk0 < tRAS) begin - $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); - end - - // tWR violation check for write - if ($time - WR_chkm[0] < tWRm) begin - $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); - end - end - - // Precharge Bank 1 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin - Act_b1 = 1'b0; - Pc_b1 = 1'b1; - RP_chk1 = $time; - $display ("%m : Precharge bank 1 at time %t", $time); - // Activate to Precharge - if ($time - RAS_chk1 < tRAS) begin - $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); - end - - // tWR violation check for write - if ($time - WR_chkm[1] < tWRm) begin - $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); - end - end - - // Precharge Bank 2 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin - Act_b2 = 1'b0; - Pc_b2 = 1'b1; - RP_chk2 = $time; - $display ("%m : Precharge bank 2 at time %t", $time); - // Activate to Precharge - if ($time - RAS_chk2 < tRAS) begin - $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); - end - - // tWR violation check for write - if ($time - WR_chkm[2] < tWRm) begin - $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); - end - end - - // Precharge Bank 3 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin - Act_b3 = 1'b0; - Pc_b3 = 1'b1; - RP_chk3 = $time; - $display ("%m : Precharge bank 3 at time %t", $time); - // Activate to Precharge - if ($time - RAS_chk3 < tRAS) begin - $display ("%m : at time %t ERROR: tRAS violation during Precharge", $time); - end - - // tWR violation check for write - if ($time - WR_chkm[3] < tWRm) begin - $display ("%m : at time %t ERROR: tWR violation during Precharge", $time); - end - end - - // Terminate a Write Immediately (if same bank or all banks) - if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin - Data_in_enable = 1'b0; - end - - // Precharge Command Pipeline for Read - if (Cas_latency_3 === 1'b1) begin - Command[2] = `PRECH; - Bank_precharge[2] = Ba; - A10_precharge[2] = Addr[10]; - end else if (Cas_latency_2 === 1'b1) begin - Command[1] = `PRECH; - Bank_precharge[1] = Ba; - A10_precharge[1] = Addr[10]; - end - end - - // Burst terminate - if (Burst_term === 1'b1) begin - // Terminate a Write Immediately - if (Data_in_enable == 1'b1) begin - Data_in_enable = 1'b0; - end - - // Terminate a Read Depend on CAS Latency - if (Cas_latency_3 === 1'b1) begin - Command[2] = `BST; - end else if (Cas_latency_2 == 1'b1) begin - Command[1] = `BST; - end - - // Display debug message - if (Debug) begin - $display ("%m : at time %t BST : Burst Terminate",$time); - end - end - - // Read, Write, Column Latch - if (Read_enable === 1'b1) begin - // Check to see if bank is open (ACT) - if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || - (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin - $display("%m : at time %t ERROR: Bank is not Activated for Read", $time); - end - - // Activate to Read or Write - if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) || - (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) || - (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) || - (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin - $display("%m : at time %t ERROR: tRCD violation during Read", $time); - end - - // CAS Latency pipeline - if (Cas_latency_3 == 1'b1) begin - Command[2] = `READ; - Col_addr[2] = Addr; - Bank_addr[2] = Ba; - end else if (Cas_latency_2 == 1'b1) begin - Command[1] = `READ; - Col_addr[1] = Addr; - Bank_addr[1] = Ba; - end - - // Read interrupt Write (terminate Write immediately) - if (Data_in_enable == 1'b1) begin - Data_in_enable = 1'b0; - - // Interrupting a Write with Autoprecharge - if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin - RW_interrupt_write[RW_interrupt_bank] = 1'b1; - RW_interrupt_counter[RW_interrupt_bank] = 0; - - // Display debug message - if (Debug) begin - $display ("%m : at time %t NOTE : Read interrupt Write with Autoprecharge", $time); - end - end - end - - // Write with Auto Precharge - if (Addr[10] == 1'b1) begin - Auto_precharge[Ba] = 1'b1; - Count_precharge[Ba] = 0; - RW_interrupt_bank = Ba; - Read_precharge[Ba] = 1'b1; - end - end - - // Write Command - if (Write_enable == 1'b1) begin - // Activate to Write - if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || - (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin - $display("%m : at time %t ERROR: Bank is not Activated for Write", $time); - end - - // Activate to Read or Write - if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) || - (Ba == 2'b01) && ($time - RCD_chk1 < tRCD) || - (Ba == 2'b10) && ($time - RCD_chk2 < tRCD) || - (Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin - $display("%m : at time %t ERROR: tRCD violation during Read", $time); - end - - // Latch Write command, Bank, and Column - Command[0] = `WRITE; - Col_addr[0] = Addr; - Bank_addr[0] = Ba; - - // Write interrupt Write (terminate Write immediately) - if (Data_in_enable == 1'b1) begin - Data_in_enable = 1'b0; - - // Interrupting a Write with Autoprecharge - if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin - RW_interrupt_write[RW_interrupt_bank] = 1'b1; - - // Display debug message - if (Debug) begin - $display ("%m : at time %t NOTE : Read Bank %h interrupt Write Bank %h with Autoprecharge", $time, Ba, RW_interrupt_bank); - end - end - end - - // Write interrupt Read (terminate Read immediately) - if (Data_out_enable == 1'b1) begin - Data_out_enable = 1'b0; - - // Interrupting a Read with Autoprecharge - if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin - RW_interrupt_read[RW_interrupt_bank] = 1'b1; - - // Display debug message - if (Debug) begin - $display ("%m : at time %t NOTE : Write Bank %h interrupt Read Bank %h with Autoprecharge", $time, Ba, RW_interrupt_bank); - end - end - end - - // Write with Auto Precharge - if (Addr[10] == 1'b1) begin - Auto_precharge[Ba] = 1'b1; - Count_precharge[Ba] = 0; - RW_interrupt_bank = Ba; - Write_precharge[Ba] = 1'b1; - end - end - - /* - Write with Auto Precharge Calculation - The device start internal precharge when: - 1. Meet minimum tRAS requirement - and 2. tWR cycle(s) after last valid data - or 3. Interrupt by a Read or Write (with or without Auto Precharge) - - Note: Model is starting the internal precharge 1 cycle after they meet all the - requirement but tRP will be compensate for the time after the 1 cycle. - */ - if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin - if ((($time - RAS_chk0 >= tRAS) && // Case 1 - (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 2 - (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) || - (RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin // Case 3 - Auto_precharge[0] = 1'b0; - Write_precharge[0] = 1'b0; - RW_interrupt_write[0] = 1'b0; - Pc_b0 = 1'b1; - Act_b0 = 1'b0; - $display ("%m : Precharge bank 0 at time %t", $time); - RP_chk0 = $time + tWRa; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); - end - end - end - if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin - if ((($time - RAS_chk1 >= tRAS) && // Case 1 - (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || // Case 2 - (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) || - (RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin // Case 3 - Auto_precharge[1] = 1'b0; - Write_precharge[1] = 1'b0; - RW_interrupt_write[1] = 1'b0; - Pc_b1 = 1'b1; - Act_b1 = 1'b0; - RP_chk1 = $time + tWRa; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); - end - end - end - if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin - if ((($time - RAS_chk2 >= tRAS) && // Case 1 - (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || // Case 2 - (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) || - (RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin // Case 3 - Auto_precharge[2] = 1'b0; - Write_precharge[2] = 1'b0; - RW_interrupt_write[2] = 1'b0; - Pc_b2 = 1'b1; - Act_b2 = 1'b0; - RP_chk2 = $time + tWRa; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); - end - end - end - if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin - if ((($time - RAS_chk3 >= tRAS) && // Case 1 - (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || // Case 2 - (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) || - (RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin // Case 3 - Auto_precharge[3] = 1'b0; - Write_precharge[3] = 1'b0; - RW_interrupt_write[3] = 1'b0; - Pc_b3 = 1'b1; - Act_b3 = 1'b0; - RP_chk3 = $time + tWRa; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); - end - end - end - - // Read with Auto Precharge Calculation - // The device start internal precharge: - // 1. Meet minimum tRAS requirement - // and 2. CAS Latency - 1 cycles before last burst - // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) - if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin - if ((($time - RAS_chk0 >= tRAS) && // Case 1 - ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 2 - (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) || - (RW_interrupt_read[0] == 1'b1)) begin // Case 3 - Pc_b0 = 1'b1; - Act_b0 = 1'b0; - $display ("%m : Precharge bank 0 at time %t", $time); - RP_chk0 = $time; - Auto_precharge[0] = 1'b0; - Read_precharge[0] = 1'b0; - RW_interrupt_read[0] = 1'b0; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); - end - end - end - if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin - if ((($time - RAS_chk1 >= tRAS) && - ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) || - (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) || - (RW_interrupt_read[1] == 1'b1)) begin - Pc_b1 = 1'b1; - Act_b1 = 1'b0; - RP_chk1 = $time; - Auto_precharge[1] = 1'b0; - Read_precharge[1] = 1'b0; - RW_interrupt_read[1] = 1'b0; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); - end - end - end - if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin - if ((($time - RAS_chk2 >= tRAS) && - ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) || - (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) || - (RW_interrupt_read[2] == 1'b1)) begin - Pc_b2 = 1'b1; - Act_b2 = 1'b0; - RP_chk2 = $time; - Auto_precharge[2] = 1'b0; - Read_precharge[2] = 1'b0; - RW_interrupt_read[2] = 1'b0; - if (Debug) begin - $display ("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); - end - end - end - if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin - if ((($time - RAS_chk3 >= tRAS) && - ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) || - (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) || - (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) || - (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) || - (RW_interrupt_read[3] == 1'b1)) begin - Pc_b3 = 1'b1; - Act_b3 = 1'b0; - RP_chk3 = $time; - Auto_precharge[3] = 1'b0; - Read_precharge[3] = 1'b0; - RW_interrupt_read[3] = 1'b0; - if (Debug) begin - $display("%m : at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); - end - end - end - - // Internal Precharge or Bst - if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks - if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin - if (Data_out_enable == 1'b1) begin - Data_out_enable = 1'b0; - end - end - end else if (Command[0] == `BST) begin // BST terminate a read to current bank - if (Data_out_enable == 1'b1) begin - Data_out_enable = 1'b0; - end - end - - if (Data_out_enable == 1'b0) begin - Dq_reg <= #tOH {data_bits{1'bz}}; - end - - // Detect Read or Write command - if (Command[0] == `READ) begin - Bank = Bank_addr[0]; - Col = Col_addr[0]; - Col_brst = Col_addr[0]; - case (Bank_addr[0]) - 2'b00 : Row = B0_row_addr; - 2'b01 : Row = B1_row_addr; - 2'b10 : Row = B2_row_addr; - 2'b11 : Row = B3_row_addr; - endcase - Burst_counter = 0; - Data_in_enable = 1'b0; - Data_out_enable = 1'b1; - end else if (Command[0] == `WRITE) begin - Bank = Bank_addr[0]; - Col = Col_addr[0]; - Col_brst = Col_addr[0]; - case (Bank_addr[0]) - 2'b00 : Row = B0_row_addr; - 2'b01 : Row = B1_row_addr; - 2'b10 : Row = B2_row_addr; - 2'b11 : Row = B3_row_addr; - endcase - Burst_counter = 0; - Data_in_enable = 1'b1; - Data_out_enable = 1'b0; - end - - // DQ buffer (Driver/Receiver) - if (Data_in_enable == 1'b1) begin // Writing Data to Memory - // Array buffer - case (Bank) - 2'b00 : Dq_dqm = Bank0 [{Row, Col}]; - 2'b01 : Dq_dqm = Bank1 [{Row, Col}]; - 2'b10 : Dq_dqm = Bank2 [{Row, Col}]; - 2'b11 : Dq_dqm = Bank3 [{Row, Col}]; - endcase - - // Dqm operation - if (Dqm[0] == 1'b0) begin - Dq_dqm [ 7 : 0] = Dq [ 7 : 0]; - end - if (Dqm[1] == 1'b0) begin - Dq_dqm [15 : 8] = Dq [15 : 8]; - end - - // Write to memory - case (Bank) - 2'b00 : Bank0 [{Row, Col}] = Dq_dqm; - 2'b01 : Bank1 [{Row, Col}] = Dq_dqm; - 2'b10 : Bank2 [{Row, Col}] = Dq_dqm; - 2'b11 : Bank3 [{Row, Col}] = Dq_dqm; - endcase - - // Display debug message - if (Dqm !== 2'b11) begin - // Record tWR for manual precharge - WR_chkm [Bank] = $time; - - if (Debug) begin - $display("%m : at time %t WRITE: Bank = %h Row = %h, Col = %h, Data = %h", $time, Bank, Row, Col, Dq_dqm); - end - end else begin - if (Debug) begin - $display("%m : at time %t WRITE: Bank = %h Row = %h, Col = %h, Data = Hi-Z due to DQM", $time, Bank, Row, Col); - end - end - - // Advance burst counter subroutine - #tHZ Burst_decode; - - end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory - // Array buffer - case (Bank) - 2'b00 : Dq_dqm = Bank0[{Row, Col}]; - 2'b01 : Dq_dqm = Bank1[{Row, Col}]; - 2'b10 : Dq_dqm = Bank2[{Row, Col}]; - 2'b11 : Dq_dqm = Bank3[{Row, Col}]; - endcase - - // Dqm operation - if (Dqm_reg0 [0] == 1'b1) begin - Dq_dqm [ 7 : 0] = 8'bz; - end - if (Dqm_reg0 [1] == 1'b1) begin - Dq_dqm [15 : 8] = 8'bz; - end - - // Display debug message - if (Dqm_reg0 !== 2'b11) begin - Dq_reg = #tAC Dq_dqm; - if (Debug) begin - $display("%m : at time %t READ : Bank = %h Row = %h, Col = %h, Data = %h", $time, Bank, Row, Col, Dq_reg); - end - end else begin - Dq_reg = #tHZ {data_bits{1'bz}}; - if (Debug) begin - $display("%m : at time %t READ : Bank = %h Row = %h, Col = %h, Data = Hi-Z due to DQM", $time, Bank, Row, Col); - end - end - - // Advance burst counter subroutine - Burst_decode; - end - end - - // Burst counter decode - task Burst_decode; - begin - // Advance Burst Counter - Burst_counter = Burst_counter + 1; - - // Burst Type - if (Mode_reg[3] == 1'b0) begin // Sequential Burst - Col_temp = Col + 1; - end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst - Col_temp[2] = Burst_counter[2] ^ Col_brst[2]; - Col_temp[1] = Burst_counter[1] ^ Col_brst[1]; - Col_temp[0] = Burst_counter[0] ^ Col_brst[0]; - end - - // Burst Length - if (Burst_length_2) begin // Burst Length = 2 - Col [0] = Col_temp [0]; - end else if (Burst_length_4) begin // Burst Length = 4 - Col [1 : 0] = Col_temp [1 : 0]; - end else if (Burst_length_8) begin // Burst Length = 8 - Col [2 : 0] = Col_temp [2 : 0]; - end else begin // Burst Length = FULL - Col = Col_temp; - end - - // Burst Read Single Write - if (Write_burst_mode == 1'b1) begin - Data_in_enable = 1'b0; - end - - // Data Counter - if (Burst_length_1 == 1'b1) begin - if (Burst_counter >= 1) begin - Data_in_enable = 1'b0; - Data_out_enable = 1'b0; - end - end else if (Burst_length_2 == 1'b1) begin - if (Burst_counter >= 2) begin - Data_in_enable = 1'b0; - Data_out_enable = 1'b0; - end - end else if (Burst_length_4 == 1'b1) begin - if (Burst_counter >= 4) begin - Data_in_enable = 1'b0; - Data_out_enable = 1'b0; - end - end else if (Burst_length_8 == 1'b1) begin - if (Burst_counter >= 8) begin - Data_in_enable = 1'b0; - Data_out_enable = 1'b0; - end - end - end - endtask - - // Timing Parameters for -7E (133 MHz @ CL2) - specify - specparam - tAH = 0.8, // Addr, Ba Hold Time - tAS = 1.5, // Addr, Ba Setup Time - tCH = 2.5, // Clock High-Level Width - tCL = 2.5, // Clock Low-Level Width - tCK = 7.0, // Clock Cycle Time - tDH = 0.8, // Data-in Hold Time - tDS = 1.5, // Data-in Setup Time - tCKH = 0.8, // CKE Hold Time - tCKS = 1.5, // CKE Setup Time - tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time - tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time - $width (posedge Clk, tCH); - $width (negedge Clk, tCL); - $period (negedge Clk, tCK); - $period (posedge Clk, tCK); - $setuphold(posedge Clk, Cke, tCKS, tCKH); - $setuphold(posedge Clk, Cs_n, tCMS, tCMH); - $setuphold(posedge Clk, Cas_n, tCMS, tCMH); - $setuphold(posedge Clk, Ras_n, tCMS, tCMH); - $setuphold(posedge Clk, We_n, tCMS, tCMH); - $setuphold(posedge Clk, Addr, tAS, tAH); - $setuphold(posedge Clk, Ba, tAS, tAH); - $setuphold(posedge Clk, Dqm, tCMS, tCMH); - $setuphold(posedge Dq_chk, Dq, tDS, tDH); - endspecify - - task get_byte; - input [31:0] addr; - output [7:0] data; - reg [1:0] bank; - reg [15:0] short; - - begin - bank = addr[24:23]; - - case(bank) - 2'b00: - short = Bank0[addr[22:1]]; - 2'b01: - short = Bank1[addr[22:1]]; - 2'b10: - short = Bank2[addr[22:1]]; - 2'b11: - short = Bank3[addr[22:1]]; - endcase // case (bank) - - // Get the byte from the short - if (!addr[0]) - data = short[15:8]; - else - data = short[7:0]; - - //$display("SDRAM addr 0x%0h, bank %0d, short 0x%0h, byte 0x%0h", addr, bank, short, data); - end - endtask // get_byte - - task set_byte; - input [31:0] addr; - input [7:0] data; - reg [1:0] bank; - reg [15:0] short; - - begin - bank = addr[24:23]; - - case(bank) - 2'b00: - short = Bank0[addr[22:1]]; - 2'b01: - short = Bank1[addr[22:1]]; - 2'b10: - short = Bank2[addr[22:1]]; - 2'b11: - short = Bank3[addr[22:1]]; - endcase // case (bank) - - // set the byte in the short - if (!addr[0]) - short[15:8] = data; - else - short[7:0] = data; - - // Write short back to memory - case(bank) - 2'b00: - Bank0[addr[22:1]] = short; - 2'b01: - Bank1[addr[22:1]] = short; - 2'b10: - Bank2[addr[22:1]] = short; - 2'b11: - Bank3[addr[22:1]] = short; - endcase // case (bank) - - end - endtask // set_byte - - task get_short; - input [31:0] addr; - output [15:0] data; - reg [1:0] bank; - reg [15:0] short; - - begin - bank = addr[24:23]; - - case(bank) - 2'b00: - short = Bank0[addr[22:1]]; - 2'b01: - short = Bank1[addr[22:1]]; - 2'b10: - short = Bank2[addr[22:1]]; - 2'b11: - short = Bank3[addr[22:1]]; - endcase // case (bank) - - data = short; - end - endtask // get_short - - task set_short; - input [31:0] addr; - input [15:0] data; - reg [1:0] bank; - begin - bank = addr[24:23]; - - // Write short back to memory - case(bank) - 2'b00: - Bank0[addr[22:1]] = data; - 2'b01: - Bank1[addr[22:1]] = data; - 2'b10: - Bank2[addr[22:1]] = data; - 2'b11: - Bank3[addr[22:1]] = data; - endcase // case (bank) - end - endtask // set_short - -endmodule diff --git a/cores/archie/bench/rtl/pix_ack_tb.v b/cores/archie/bench/rtl/pix_ack_tb.v deleted file mode 100644 index e1aa5bc..0000000 --- a/cores/archie/bench/rtl/pix_ack_tb.v +++ /dev/null @@ -1,68 +0,0 @@ -`timescale 1ns / 1ps -/* pix_ack_tb.v - - Copyright (c) 2012-2014, Stephen J. Leary - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -module pix_ack_tb; - - wire pix_ack; - reg CLK = 0; - reg [4:0] counter = 0; - wire [2:0] pix_shift_count; - wire [3:2] vidc_cr; - - initial begin - $display ("ticks: vidc_cr pix_shift_count pix_ack"); - $monitor ("%b %b %b",vidc_cr, pix_shift_count, pix_ack); - - // Initialize Inputs - CLK = 0; - - #315; - - $finish(); - - end - - always - begin - #5; CLK = ~CLK; - end - - always @(posedge CLK) begin - - counter <= counter + 4'd1; - - end - -assign vidc_cr[3:2] = counter[4:3]; -assign pix_shift_count[2:0] = counter[2:0]; -assign pix_ack = ((pix_shift_count[2] & vidc_cr[3]) | ( vidc_cr[2] & vidc_cr[3]) | (pix_shift_count[0] & pix_shift_count[1] & pix_shift_count[2]) | (pix_shift_count[1] & pix_shift_count[2] & vidc_cr[2])); - - -endmodule - diff --git a/cores/archie/bench/rtl/sdram_interface.cpp b/cores/archie/bench/rtl/sdram_interface.cpp deleted file mode 100644 index 295dcc3..0000000 --- a/cores/archie/bench/rtl/sdram_interface.cpp +++ /dev/null @@ -1,111 +0,0 @@ -#include // Defines common routines -#include "Vsdram_interface.h" -#include "verilated_vcd_c.h" -#include -#include -#include -#include -#include -#include - -Vsdram_interface *uut; // Instantiation of module - -vluint64_t main_time = 0; // Current simulation time -// This is a 64-bit integer to reduce wrap over issues and -// allow modulus. You can also use a double, if you wish. -double sc_time_stamp () { // Called by $time in Verilog - return main_time; // converts to double, to match - // what SystemC does -} - -class Edge -{ -public: - Edge() - { - m_NegEdge = false; - m_PosEdge = false; - m_LastValue = false; - } - - void Update(bool value) - { - m_PosEdge = value & ~ m_LastValue; - m_NegEdge = ~value & m_LastValue; - m_LastValue = value; - } - - bool PosEdge() { return m_PosEdge; } - bool NegEdge() { return m_NegEdge; } - -private: - bool m_NegEdge; - bool m_PosEdge; - bool m_LastValue; -}; - -int delay = 0; - -int main(int argc, char** argv) { - - Edge cpuclk; - Edge ramclk; - - Verilated::commandArgs(argc, argv); // Remember args - uut = new Vsdram_interface; // Create instance - - Verilated::traceEverOn(true); - VerilatedVcdC* tfp = new VerilatedVcdC; - uut->trace(tfp, 99); - tfp->open("sdram.vcd"); - - while (!Verilated::gotFinish()) - { - if ((main_time % 2) == 0) - { - uut->DRAM_CLK = uut->DRAM_CLK ? 0 : 1; // Toggle clock - } - - if ((main_time % 8) == 0) - { - uut->wb_clk = uut->wb_clk ? 0 : 1; // Toggle clock - } - - cpuclk.Update(uut->wb_clk); - ramclk.Update(uut->DRAM_CLK); - - uut->eval(); // Evaluate model - tfp->dump (main_time); - - if (uut->wb_ready) - { - if (cpuclk.PosEdge()) - { - delay++; - if (uut->wb_ack) - { - delay = 0; - std::cout << uut->wb_dat_o << std::endl; - uut->wb_stb = 0; - uut->wb_cyc = 0; - uut->wb_we = 0; - } - else if (delay > 8) - { - uut->wb_stb = 1; - uut->wb_cyc = 1; - uut->wb_we = 0; - } - - - } - } - - main_time++; // Time passes... - } - - uut->final(); // Done simulating - tfp->close(); - delete uut; - -} diff --git a/cores/archie/bench/rtl/sdram_interface.v b/cores/archie/bench/rtl/sdram_interface.v deleted file mode 100644 index 51ac8b0..0000000 --- a/cores/archie/bench/rtl/sdram_interface.v +++ /dev/null @@ -1,109 +0,0 @@ -`timescale 1ns / 1ps -/* sdram_interface.v - - Copyright (c) 2015, Stephen J. Leary - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -module sdram_interface( - - // Inputs - input DRAM_CLK, - input RESET, - - // cpu/chipset interface - input wb_clk, // 32MHz chipset clock to which sdram state machine is synchonized - input [31:0] wb_dat_i, // data input from chipset/cpu - output [31:0] wb_dat_o, // data output to chipset/cpu - output wb_ack, - input [23:0] wb_adr, // lower 2 bits are ignored. - input [3:0] wb_sel, // - input [2:0] wb_cti, // cycle type. - input wb_stb, // - input wb_cyc, // cpu/chipset requests cycle - input wb_we, // cpu/chipset requests write - output wb_ready -); - - -sdram_top uut( - - // wishbone interface - .wb_clk ( wb_clk ), - .wb_stb ( wb_stb ), - .wb_cyc ( wb_cyc ), - .wb_we ( wb_wr ), - .wb_ack ( wb_ack ), - .wb_sel ( wb_sel ), - .wb_adr ( wb_adr ), - .wb_dat_i ( wb_dat_i ), - .wb_dat_o ( wb_dat_o ), - .wb_cti ( wb_cti ), - - // SDRAM Interface - .sd_clk ( DRAM_CLK ), - .sd_rst ( RESET ), - .sd_cke ( DRAM_CKE ), - .sd_dq ( DRAM_DQ ), - .sd_addr ( DRAM_A ), - .sd_dqm ( DRAM_DQM ), - .sd_cs_n ( DRAM_CS_N ), - .sd_ba ( DRAM_BA ), - .sd_we_n ( DRAM_WE_N ), - .sd_ras_n ( DRAM_RAS_N ), - .sd_cas_n ( DRAM_CAS_N ), - .sd_ready ( wb_ready ) - -); - - // SDRAM -wire [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits -wire [12:0] DRAM_A; // SDRAM Address bus 13 Bits -wire [1:0] DRAM_DQM; // SDRAM Low-byte Data Mask -wire DRAM_WE_N; // SDRAM Write Enable -wire DRAM_CAS_N; // SDRAM Column Address Strobe -wire DRAM_RAS_N; // SDRAM Row Address Strobe -wire DRAM_CS_N; // SDRAM Chip Select -wire [1:0] DRAM_BA; // SDRAM Bank Address -wire DRAM_CLK; // SDRAM Clock -wire DRAM_CKE; // SDRAM Clock Enable - -mt48lc16m16a2 SDRAM( - - .Dq ( DRAM_DQ ), - .Addr ( DRAM_A ), - .Ba ( DRAM_BA ), - .Clk ( DRAM_CLK ), - .Cke ( DRAM_CKE ), - .Cs_n ( DRAM_CS_N ), - .Ras_n ( DRAM_RAS_N), - .Cas_n ( DRAM_CAS_N), - .We_n ( DRAM_WE_N ), - .Dqm ( DRAM_DQM ) - -); - -endmodule - diff --git a/cores/archie/bench/rtl/sdram_tb.v b/cores/archie/bench/rtl/sdram_tb.v deleted file mode 100644 index 474be43..0000000 --- a/cores/archie/bench/rtl/sdram_tb.v +++ /dev/null @@ -1,1416 +0,0 @@ -`timescale 1ns / 1ps -/* sdram_tb.v - - Copyright (c) 2012-2014, Stephen J. Leary - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -module sdram_tb; - - // Inputs - reg CLK128M; - reg CLK32M; - - reg reset; - - // SDRAM - wire [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits - wire [12:0] DRAM_A; // SDRAM Address bus 13 Bits - wire [1:0] DRAM_DQM; // SDRAM Low-byte Data Mask - wire DRAM_WE_N; // SDRAM Write Enable - wire DRAM_CAS_N; // SDRAM Column Address Strobe - wire DRAM_RAS_N; // SDRAM Row Address Strobe - wire DRAM_CS_N; // SDRAM Chip Select - wire [1:0] DRAM_BA; // SDRAM Bank Address - wire DRAM_CLK; // SDRAM Clock - wire DRAM_CKE; // SDRAM Clock Enable - - reg [31:0] wb_data_in = 0; - wire [31:0] wb_data_out; - wire wb_ack; - reg [23:0] wb_address; - reg [3:0] wb_sel = 4'b1111; - reg [2:0] wb_cti = 4'b000; - reg wb_cyc = 1'b0; - reg wb_stb = 1'b0; - reg wb_wr = 1'b0; - -localparam RASCAS_DELAY = 3'd3; // tRCD=20ns -> 3 cycles@128MHz -localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8 -localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved -localparam CAS_LATENCY = 3'd3; // 2/3 allowed -localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed -localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write -localparam WRITE_BURST = 1'b0; // 0= write burst enabled, 1=only single access write - -localparam MODE = { 3'b000, WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; - - sdram_top uut( - - // wishbone interface - .wb_clk ( CLK32M ), - .wb_stb ( wb_stb ), - .wb_cyc ( wb_cyc ), - .wb_we ( wb_wr ), - .wb_ack ( wb_ack ), - - .wb_sel ( wb_sel ), - .wb_adr ( wb_address ), - .wb_dat_i ( wb_data_in ), - .wb_dat_o ( wb_data_out ), - //.wb_cti_i ( wb_cti ), - - // SDRAM Interface - .sd_clk ( CLK128M ), - .sd_rst ( reset ), - .sd_cke ( DRAM_CKE ), - - .sd_dq ( DRAM_DQ ), - .sd_addr ( DRAM_A ), - .sd_dqm ( DRAM_DQM ), - .sd_cs_n ( DRAM_CS_N ), - .sd_ba ( DRAM_BA ), - .sd_we_n ( DRAM_WE_N ), - .sd_ras_n ( DRAM_RAS_N ), - .sd_cas_n ( DRAM_CAS_N ), - .sd_ready ( ready ) - - ); - - mt48lc16m16a2 SDRAM( - - .Dq ( DRAM_DQ ), - .Addr ( DRAM_A ), - .Ba ( DRAM_BA ), - .Clk ( CLK128M ), - .Cke ( DRAM_CKE ), - .Cs_n ( DRAM_CS_N ), - .Ras_n ( DRAM_RAS_N), - .Cas_n ( DRAM_CAS_N), - .We_n ( DRAM_WE_N ), - .Dqm ( DRAM_DQM ) - ); - - initial begin - - $dumpfile("sdram.vcd"); - $dumpvars(0, sdram_tb); - - $display ("ticks: CLK"); - $monitor ("%g %b %b %h", $time, CLK32M, wb_wr, wb_data_out); - - // Initialize Inputs - CLK128M = 0; - CLK32M = 0; - reset = 1; - - wb_stb = 1'b0; - wb_cyc = 1'b0; - wb_wr = 1'b0; - wb_address = 0; - - #50; - reset = 0; - - wait(ready); - - wait(~CLK32M); - wait(CLK32M); - wb_data_in = 32'hDEADBEEF; - wb_address = 0; - wb_sel = 4'b1011; - wb_wr = 1'b1; - wb_cti = 3'b000; - wb_stb = 1'b1; - wb_cyc = 1'b1; - wait(wb_ack); - wait(~CLK32M); - wait(CLK32M); - wb_wr = 1'b0; - wb_cti = 3'b010; - wb_stb = 1'b0; - wb_cyc = 1'b0; - wait(wb_ack); - wait(~CLK32M); - wait(CLK32M); - wb_wr = 1'b0; - wb_stb = 1'b1; - wb_cyc = 1'b1; - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - wb_address = wb_address + 2; - wait(~wb_ack); - wait(wb_ack); - - - #30; - - $writememh("bank0.hex", SDRAM.Bank0); - //$writememh("bank1.hex", SDRAM.Bank1); - //$writememh("bank2.hex", SDRAM.Bank2); - //$writememh("bank3.hex", SDRAM.Bank3); - $finish(); - - end - - always - begin - #4; CLK128M = ~CLK128M; - end - - always - begin - #15; CLK32M = ~CLK32M; - end - - -endmodule - diff --git a/cores/archie/bench/rtl/sram_byte_en.v b/cores/archie/bench/rtl/sram_byte_en.v deleted file mode 100644 index f766e06..0000000 --- a/cores/archie/bench/rtl/sram_byte_en.v +++ /dev/null @@ -1,84 +0,0 @@ -////////////////////////////////////////////////////////////////// -// // -// Generic Library SRAM with per byte write enable // -// // -// This file is part of the Amber project // -// http://www.opencores.org/project,amber // -// // -// Description // -// Configurable depth and width. The DATA_WIDTH must be a // -// multiple of 8. // -// // -// Author(s): // -// - Conor Santifort, csantifort.amber@gmail.com // -// // -////////////////////////////////////////////////////////////////// -// // -// Copyright (C) 2010 Authors and OPENCORES.ORG // -// // -// This source file may be used and distributed without // -// restriction provided that this copyright statement is not // -// removed from the file and that any derivative work contains // -// the original copyright notice and the associated disclaimer. // -// // -// This source file is free software; you can redistribute it // -// and/or modify it under the terms of the GNU Lesser General // -// Public License as published by the Free Software Foundation; // -// either version 2.1 of the License, or (at your option) any // -// later version. // -// // -// This source is distributed in the hope that it will be // -// useful, but WITHOUT ANY WARRANTY; without even the implied // -// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // -// PURPOSE. See the GNU Lesser General Public License for more // -// details. // -// // -// You should have received a copy of the GNU Lesser General // -// Public License along with this source; if not, download it // -// from http://www.opencores.org/lgpl.shtml // -// // -////////////////////////////////////////////////////////////////// - - -module sram_byte_en -#( -parameter DATA_WIDTH = 128, -parameter ADDRESS_WIDTH = 7 -) - -( -input i_clk, -input [DATA_WIDTH-1:0] i_write_data, -input i_write_enable, -input [ADDRESS_WIDTH-1:0] i_address, -input [DATA_WIDTH/8-1:0] i_byte_enable, -output reg [DATA_WIDTH-1:0] o_read_data - ); - -reg [DATA_WIDTH-1:0] mem [0:2**ADDRESS_WIDTH-1]; -integer i; - -always @(posedge i_clk) - begin - // read - o_read_data <= i_write_enable ? {DATA_WIDTH{1'd0}} : mem[i_address]; - - // write - if (i_write_enable) - for (i=0;i0; log2=log2+1) - value = value>>1; - - end - endfunction // for - - // increment -- add one to value modulo depth. - function [log2_depth-1:0] increment; - - input [log2_depth-1:0] value; - - begin - if (value == depth-1) - increment = 0; - - else - increment = value+1; - - end - endfunction // if - - // writing -- true when we write to the RAM. - wire writing = wr_enable && (rd_enable || !full); - - - // reading -- true when we are reading from the RAM. - wire reading = rd_enable && !empty; - - - // rd_ptr -- the read pointer. - reg [log2_depth-1:0] rd_ptr; - - - // next_rd_ptr -- the next value for the read pointer. - // We need to name this combinational value because it - // is needed to use the write-before-read style RAM. - reg [log2_depth-1:0] next_rd_ptr; - - always @(*) - if (reset) - next_rd_ptr = 0; - - else if (reading) - next_rd_ptr = increment(rd_ptr); - - else - next_rd_ptr = rd_ptr; - - - always @(posedge clk) - rd_ptr <= next_rd_ptr; - - - // wr_ptr -- the write pointer - reg [log2_depth-1:0] wr_ptr; - - - // next_wr_ptr -- the next value for the write pointer. - reg [log2_depth-1:0] next_wr_ptr; - - always @(*) - if (reset) - next_wr_ptr = 0; - - else if (writing) - next_wr_ptr = increment(wr_ptr); - - else - next_wr_ptr = wr_ptr; - - - always @(posedge clk) - wr_ptr <= next_wr_ptr; - - - // count -- the number of valid entries in the FIFO. - always @(posedge clk) - if (reset) - count <= 0; - - else if (writing && !reading) - count <= count+1; - - else if (reading && !writing) - count <= count-1; - - - // empty -- true if the FIFO is empty. - // Note that this doesn't depend on count so if the count - // output is unused the logic for computing the count can - // be optimized away. - always @(posedge clk) - if (reset) - empty <= 1; - - else if (reading && next_wr_ptr == next_rd_ptr && !full) - empty <= 1; - - else - if (writing && !reading) - empty <= 0; - - - // full -- true if the FIFO is full. - // Again, this is not dependent on count. - always @(posedge clk) - if (reset) - full <= 0; - - else if (writing && next_wr_ptr == next_rd_ptr) - full <= 1; - - else if (reading && !writing) - full <= 0; - - - // We need to infer a write first style RAM so that when - // the FIFO is empty the write data can flow through to - // the read side and be available the next clock cycle. - reg [width-1:0] mem [depth-1:0]; - - always @(posedge clk) - begin - if (writing) - mem[wr_ptr] <= wr_data; - - rd_ptr <= next_rd_ptr; - rd_data <= mem[rd_ptr]; - end - - - - - endmodule \ No newline at end of file diff --git a/cores/archie/bench/rtl/test.v b/cores/archie/bench/rtl/test.v deleted file mode 100644 index c959a25..0000000 --- a/cores/archie/bench/rtl/test.v +++ /dev/null @@ -1,269 +0,0 @@ -module test -( - input clk, // bus clock - input [7:0] a, // address in - (*KEEP="TRUE"*) output reg [7:0] q // data out -); - -always @(posedge clk) begin - case (a) - 8'd0000: q <= 8'h00; - 8'd0001: q <= 8'h01; - 8'd0002: q <= 8'h02; - 8'd0003: q <= 8'h03; - 8'd0004: q <= 8'h04; - 8'd0005: q <= 8'h05; - 8'd0006: q <= 8'h06; - 8'd0007: q <= 8'h07; - 8'd0008: q <= 8'h08; - 8'd0009: q <= 8'h09; - 8'd0010: q <= 8'h0a; - 8'd0011: q <= 8'h0b; - 8'd0012: q <= 8'h0c; - 8'd0013: q <= 8'h0d; - 8'd0014: q <= 8'h0e; - 8'd0015: q <= 8'h0f; - 8'd0016: q <= 8'h10; - 8'd0017: q <= 8'h11; - 8'd0018: q <= 8'h12; - 8'd0019: q <= 8'h13; - 8'd0020: q <= 8'h14; - 8'd0021: q <= 8'h15; - 8'd0022: q <= 8'h16; - 8'd0023: q <= 8'h17; - 8'd0024: q <= 8'h18; - 8'd0025: q <= 8'h19; - 8'd0026: q <= 8'h1a; - 8'd0027: q <= 8'h1b; - 8'd0028: q <= 8'h1c; - 8'd0029: q <= 8'h1d; - 8'd0030: q <= 8'h1e; - 8'd0031: q <= 8'h1f; - 8'd0032: q <= 8'h20; - 8'd0033: q <= 8'h21; - 8'd0034: q <= 8'h22; - 8'd0035: q <= 8'h23; - 8'd0036: q <= 8'h24; - 8'd0037: q <= 8'h25; - 8'd0038: q <= 8'h26; - 8'd0039: q <= 8'h27; - 8'd0040: q <= 8'h28; - 8'd0041: q <= 8'h29; - 8'd0042: q <= 8'h2a; - 8'd0043: q <= 8'h2b; - 8'd0044: q <= 8'h2c; - 8'd0045: q <= 8'h2d; - 8'd0046: q <= 8'h2e; - 8'd0047: q <= 8'h2f; - 8'd0048: q <= 8'h30; - 8'd0049: q <= 8'h31; - 8'd0050: q <= 8'h32; - 8'd0051: q <= 8'h33; - 8'd0052: q <= 8'h34; - 8'd0053: q <= 8'h35; - 8'd0054: q <= 8'h36; - 8'd0055: q <= 8'h37; - 8'd0056: q <= 8'h38; - 8'd0057: q <= 8'h39; - 8'd0058: q <= 8'h3a; - 8'd0059: q <= 8'h3b; - 8'd0060: q <= 8'h3c; - 8'd0061: q <= 8'h3d; - 8'd0062: q <= 8'h3e; - 8'd0063: q <= 8'h3f; - 8'd0064: q <= 8'h40; - 8'd0065: q <= 8'h41; - 8'd0066: q <= 8'h42; - 8'd0067: q <= 8'h43; - 8'd0068: q <= 8'h44; - 8'd0069: q <= 8'h45; - 8'd0070: q <= 8'h46; - 8'd0071: q <= 8'h47; - 8'd0072: q <= 8'h48; - 8'd0073: q <= 8'h49; - 8'd0074: q <= 8'h4a; - 8'd0075: q <= 8'h4b; - 8'd0076: q <= 8'h4c; - 8'd0077: q <= 8'h4d; - 8'd0078: q <= 8'h4e; - 8'd0079: q <= 8'h4f; - 8'd0080: q <= 8'h50; - 8'd0081: q <= 8'h51; - 8'd0082: q <= 8'h52; - 8'd0083: q <= 8'h53; - 8'd0084: q <= 8'h54; - 8'd0085: q <= 8'h55; - 8'd0086: q <= 8'h56; - 8'd0087: q <= 8'h57; - 8'd0088: q <= 8'h58; - 8'd0089: q <= 8'h59; - 8'd0090: q <= 8'h5a; - 8'd0091: q <= 8'h5b; - 8'd0092: q <= 8'h5c; - 8'd0093: q <= 8'h5d; - 8'd0094: q <= 8'h5e; - 8'd0095: q <= 8'h5f; - 8'd0096: q <= 8'h60; - 8'd0097: q <= 8'h61; - 8'd0098: q <= 8'h62; - 8'd0099: q <= 8'h63; - 8'd0100: q <= 8'h64; - 8'd0101: q <= 8'h65; - 8'd0102: q <= 8'h66; - 8'd0103: q <= 8'h67; - 8'd0104: q <= 8'h68; - 8'd0105: q <= 8'h69; - 8'd0106: q <= 8'h6a; - 8'd0107: q <= 8'h6b; - 8'd0108: q <= 8'h6c; - 8'd0109: q <= 8'h6d; - 8'd0110: q <= 8'h6e; - 8'd0111: q <= 8'h6f; - 8'd0112: q <= 8'h70; - 8'd0113: q <= 8'h71; - 8'd0114: q <= 8'h72; - 8'd0115: q <= 8'h73; - 8'd0116: q <= 8'h74; - 8'd0117: q <= 8'h75; - 8'd0118: q <= 8'h76; - 8'd0119: q <= 8'h77; - 8'd0120: q <= 8'h78; - 8'd0121: q <= 8'h79; - 8'd0122: q <= 8'h7a; - 8'd0123: q <= 8'h7b; - 8'd0124: q <= 8'h7c; - 8'd0125: q <= 8'h7d; - 8'd0126: q <= 8'h7e; - 8'd0127: q <= 8'h7f; - 8'd0128: q <= 8'h80; - 8'd0129: q <= 8'h81; - 8'd0130: q <= 8'h82; - 8'd0131: q <= 8'h83; - 8'd0132: q <= 8'h84; - 8'd0133: q <= 8'h85; - 8'd0134: q <= 8'h86; - 8'd0135: q <= 8'h87; - 8'd0136: q <= 8'h88; - 8'd0137: q <= 8'h89; - 8'd0138: q <= 8'h8a; - 8'd0139: q <= 8'h8b; - 8'd0140: q <= 8'h8c; - 8'd0141: q <= 8'h8d; - 8'd0142: q <= 8'h8e; - 8'd0143: q <= 8'h8f; - 8'd0144: q <= 8'h90; - 8'd0145: q <= 8'h91; - 8'd0146: q <= 8'h92; - 8'd0147: q <= 8'h93; - 8'd0148: q <= 8'h94; - 8'd0149: q <= 8'h95; - 8'd0150: q <= 8'h96; - 8'd0151: q <= 8'h97; - 8'd0152: q <= 8'h98; - 8'd0153: q <= 8'h99; - 8'd0154: q <= 8'h9a; - 8'd0155: q <= 8'h9b; - 8'd0156: q <= 8'h9c; - 8'd0157: q <= 8'h9d; - 8'd0158: q <= 8'h9e; - 8'd0159: q <= 8'h9f; - 8'd0160: q <= 8'ha0; - 8'd0161: q <= 8'ha1; - 8'd0162: q <= 8'ha2; - 8'd0163: q <= 8'ha3; - 8'd0164: q <= 8'ha4; - 8'd0165: q <= 8'ha5; - 8'd0166: q <= 8'ha6; - 8'd0167: q <= 8'ha7; - 8'd0168: q <= 8'ha8; - 8'd0169: q <= 8'ha9; - 8'd0170: q <= 8'haa; - 8'd0171: q <= 8'hab; - 8'd0172: q <= 8'hac; - 8'd0173: q <= 8'had; - 8'd0174: q <= 8'hae; - 8'd0175: q <= 8'haf; - 8'd0176: q <= 8'hb0; - 8'd0177: q <= 8'hb1; - 8'd0178: q <= 8'hb2; - 8'd0179: q <= 8'hb3; - 8'd0180: q <= 8'hb4; - 8'd0181: q <= 8'hb5; - 8'd0182: q <= 8'hb6; - 8'd0183: q <= 8'hb7; - 8'd0184: q <= 8'hb8; - 8'd0185: q <= 8'hb9; - 8'd0186: q <= 8'hba; - 8'd0187: q <= 8'hbb; - 8'd0188: q <= 8'hbc; - 8'd0189: q <= 8'hbd; - 8'd0190: q <= 8'hbe; - 8'd0191: q <= 8'hbf; - 8'd0192: q <= 8'hc0; - 8'd0193: q <= 8'hc1; - 8'd0194: q <= 8'hc2; - 8'd0195: q <= 8'hc3; - 8'd0196: q <= 8'hc4; - 8'd0197: q <= 8'hc5; - 8'd0198: q <= 8'hc6; - 8'd0199: q <= 8'hc7; - 8'd0200: q <= 8'hc8; - 8'd0201: q <= 8'hc9; - 8'd0202: q <= 8'hca; - 8'd0203: q <= 8'hcb; - 8'd0204: q <= 8'hcc; - 8'd0205: q <= 8'hcd; - 8'd0206: q <= 8'hce; - 8'd0207: q <= 8'hcf; - 8'd0208: q <= 8'hd0; - 8'd0209: q <= 8'hd1; - 8'd0210: q <= 8'hd2; - 8'd0211: q <= 8'hd3; - 8'd0212: q <= 8'hd4; - 8'd0213: q <= 8'hd5; - 8'd0214: q <= 8'hd6; - 8'd0215: q <= 8'hd7; - 8'd0216: q <= 8'hd8; - 8'd0217: q <= 8'hd9; - 8'd0218: q <= 8'hda; - 8'd0219: q <= 8'hdb; - 8'd0220: q <= 8'hdc; - 8'd0221: q <= 8'hdd; - 8'd0222: q <= 8'hde; - 8'd0223: q <= 8'hdf; - 8'd0224: q <= 8'he0; - 8'd0225: q <= 8'he1; - 8'd0226: q <= 8'he2; - 8'd0227: q <= 8'he3; - 8'd0228: q <= 8'he4; - 8'd0229: q <= 8'he5; - 8'd0230: q <= 8'he6; - 8'd0231: q <= 8'he7; - 8'd0232: q <= 8'he8; - 8'd0233: q <= 8'he9; - 8'd0234: q <= 8'hea; - 8'd0235: q <= 8'heb; - 8'd0236: q <= 8'hec; - 8'd0237: q <= 8'hed; - 8'd0238: q <= 8'hee; - 8'd0239: q <= 8'hef; - 8'd0240: q <= 8'hf0; - 8'd0241: q <= 8'hf1; - 8'd0242: q <= 8'hf2; - 8'd0243: q <= 8'hf3; - 8'd0244: q <= 8'hf4; - 8'd0245: q <= 8'hf5; - 8'd0246: q <= 8'hf6; - 8'd0247: q <= 8'hf7; - 8'd0248: q <= 8'hf8; - 8'd0249: q <= 8'hf9; - 8'd0250: q <= 8'hfa; - 8'd0251: q <= 8'hfb; - 8'd0252: q <= 8'hfc; - 8'd0253: q <= 8'hfd; - 8'd0254: q <= 8'hfe; - 8'd0255: q <= 8'hff; - endcase -end - -endmodule diff --git a/cores/archie/bench/rtl/vidc_fifo_tb.v b/cores/archie/bench/rtl/vidc_fifo_tb.v deleted file mode 100644 index d1b7b95..0000000 --- a/cores/archie/bench/rtl/vidc_fifo_tb.v +++ /dev/null @@ -1,145 +0,0 @@ -`timescale 1ns / 1ps -/* vidc_fifo_tb.v - - Copyright (c) 2012-2014, Stephen J. Leary - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -module vidc_fifo_tb; - - // Inputs - reg CLK32M; - reg CLK25M; - reg reset; - reg wr_en; - reg rd_en; - - reg [31:0] din; - wire [7:0] dout; - - wire [2:0] wr_ptr; - wire [4:0] rd_ptr; - - // Instantiate the Unit Under Test (UUT) - vidc_fifo UUT ( - .rst(rst), - .wr_clk(CLK32M), - .rd_clk(CLK25M), - - .wr_en(wr_en), - .rd_en(rd_en), - - .din(din), - .dout(dout), - - .wr_ptr(wr_ptr), - .rd_ptr(rd_ptr) - - ); - - initial begin - - $dumpfile("vidc_fifo.vcd"); - $dumpvars(0, UUT); - - $display ("ticks:"); - $monitor ("%g %b %b %h %h %h", $time, CLK32M, rd_en, rd_ptr, wr_ptr, dout); - - // Initialize Inputs - CLK32M = 0; - CLK25M = 0; - reset = 1; - wr_en = 0; - rd_en = 0; - din = 32'h00AA_00FF; - #150; - reset = 0; - #135; - wr_en = 1; - #30; - wr_en = 0; - #120; - din = 32'h0000_0000; - wr_en = 1; - #30; - wr_en = 0; - #120; - wr_en = 1; - #30; - wr_en = 0; - #120; - din = 32'h0000_0000; - wr_en = 1; - #30; - wr_en = 0; - #120; - wr_en = 1; - #30; - wr_en = 0; - #120; - din = 32'h0000_0000; - wr_en = 1; - #30; - wr_en = 0; - #120; - wait(CLK25M); - #35; - rd_en = 1; - #40; - rd_en = 0; - #40; - rd_en = 1; - #40; - rd_en = 0; - #400; - - #40; - rd_en = 1; - #40; - rd_en = 0; - #400; - - #40; - rd_en = 1; - #40; - rd_en = 0; - #400; - - $finish(); - - end - - always - begin - #20; CLK25M = ~CLK25M; - end - - always - begin - #15; CLK32M = ~CLK32M; - end - -endmodule - diff --git a/cores/archie/bench/rtl/vidc_tb.v b/cores/archie/bench/rtl/vidc_tb.v deleted file mode 100644 index ad2aead..0000000 --- a/cores/archie/bench/rtl/vidc_tb.v +++ /dev/null @@ -1,148 +0,0 @@ -`timescale 1ns / 1ps -/* archimedes_tb.v - - Copyright (c) 2012-2014, Stephen J. Leary - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -module vidc_tb; - - // Inputs - reg CLK32M; - reg CLK25M; - reg reset; - reg vidak; - reg[31:0] viddat; - - wire vidrq; - wire flybk; - wire hsync; - - // Instantiate the Unit Under Test (UUT) - vidc UUT ( - .clkcpu(CLK32M), - .clkpix(CLK25M), - .rst_i(reset), - - .viddat(viddat), - .vidrq(vidrq), - .vidak(vidak), - .flybk(flybk), - .hsync(hsync) - - ); - - initial begin - - $dumpfile("vidc.vcd"); - $dumpvars(0, UUT); - - $display ("ticks:"); - - // Initialize Inputs - CLK32M = 0; - CLK25M = 0; - reset = 1; - vidak = 0; - #10; - reset = 0; - wait(vidrq); - $monitor ("%g %b %b %b %b %b %b %b %h %b", $time, CLK32M, vidrq, vidak, hsync, flybk, UUT.cur_load, UUT.vid_load, UUT.dma_count, UUT.vid_fifo_can_load); - #120; - vidak = 1; - #30; - vidak = 0; - #30; - vidak = 1; - #30; - vidak = 0; - #30; - vidak = 1; - #30; - vidak = 0; - #30; - vidak = 1; - #30; - vidak = 0; - #30; - wait(vidrq); - viddat = 32'h00AA00FF; - #120; - vidak = 1; - #30; - vidak = 0; - viddat = 32'h0055_0055; - #30; - vidak = 1; - #30; - viddat = 32'h00000000; - vidak = 0; - #30; - vidak = 1; - #30; - vidak = 0; - #30; - vidak = 1; - #30; - vidak = 0; - #30; - wait(vidrq); - #120; - vidak = 1; - #30; - vidak = 0; - #30; - vidak = 1; - #30; - vidak = 0; - #30; - vidak = 1; - #30; - vidak = 0; - #30; - vidak = 1; - #30; - vidak = 0; - #30; - - - - #60000; - $finish(); - - end - - always - begin - #20; CLK25M = ~CLK25M; - end - - always - begin - #15; CLK32M = ~CLK32M; - end - -endmodule - diff --git a/cores/archie/bench/tests.workspace b/cores/archie/bench/tests.workspace deleted file mode 100644 index 97beca4..0000000 --- a/cores/archie/bench/tests.workspace +++ /dev/null @@ -1,23 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - -