diff --git a/cores/mist/blitter.v b/cores/mist/blitter.v
index 571ccf2..0c66004 100644
--- a/cores/mist/blitter.v
+++ b/cores/mist/blitter.v
@@ -141,7 +141,7 @@ reg init;
 reg wait4bus;
 
 // counter for cooperative (non-hog) bus access
-reg [5:0] bus_coop_cnt /* synthesis noprune */;
+reg [5:0] bus_coop_cnt;
 
 reg bus_owned;
 
diff --git a/cores/mist/ethernec.v b/cores/mist/ethernec.v
index 8a1ddc1..4cef0e8 100644
--- a/cores/mist/ethernec.v
+++ b/cores/mist/ethernec.v
@@ -61,15 +61,15 @@ assign status = { statusCode, 5'h00, tbcr == tx_w_cnt, isr[1:0], tbcr };
 // ----- bus interface signals as wired up on the ethernec/netusbee ------
 // sel[0] = 0xfa0000 -> normal read
 // sel[1] = 0xfb0000 -> write through address bus
-wire ne_read = sel[0] /* synthesis keep */;
-wire ne_write = sel[1] /* synthesis keep */;
-wire [4:0] ne_addr = addr[12:8] /* synthesis keep */;
-wire [7:0] ne_wdata = addr[7:0] /* synthesis keep */;
+wire ne_read = sel[0];
+wire ne_write = sel[1];
+wire [4:0] ne_addr = addr[12:8];
+wire [7:0] ne_wdata = addr[7:0];
 reg [7:0] ne_rdata;
 assign dout = { ne_rdata, 8'h00 };
 
 // ---------- ne2000 internal registers -------------
-reg reset /* synthesis noprune */;
+reg reset;
 reg [7:0]  cr;             // ne command register
 reg [7:0]  isr;            // ne interrupt service register
 reg [7:0]  imr;            // interrupt mask register
@@ -84,7 +84,7 @@ reg [7:0]  pstop;          // rx buffer ring stop page
 reg [7:0]  par [5:0];      // 6 byte mac address register
 reg [7:0]  mar [7:0];      // 8 byte multicast hash register
 reg [15:0] rbcr;           // receiver byte count register
-reg [15:0] rsar /* synthesis noprune */;           // receiver address register
+reg [15:0] rsar;           // receiver address register
 reg [15:0] tbcr;           // transmitter byte count register
 
 
@@ -120,8 +120,8 @@ end
 // ------------- set local mac address ------------
 
 // mac address from io controller
-reg [7:0] mac [5:0] /* synthesis noprune */;
-reg [2:0] mac_cnt /* synthesis noprune */;
+reg [7:0] mac [5:0];
+reg [2:0] mac_cnt;
 
 always @(negedge mac_strobe or posedge mac_begin) begin
 	if(mac_begin)
@@ -180,8 +180,8 @@ reg [1:0] rx_w_state;
 // Several sources can write into the rx_buffer. The user_io SPI client receiving 
 // data from the io controller or the ethernec core itself setting the mac address
 // or adding the rx header 
-wire rx_write_clk = rx_strobe || int_strobe /* synthesis keep */;
-wire rx_write_begin = (rx_beginD && !rx_beginD2) || int_begin /* synthesis keep */;
+wire rx_write_clk = rx_strobe || int_strobe;
+wire rx_write_begin = (rx_beginD && !rx_beginD2) || int_begin;
 
 reg rx_lastByte;
 
@@ -194,7 +194,7 @@ always @(negedge clk)
 	rx_new_pageD <= rx_new_page;
 	
 // -------- dummy page counter ---------
-reg [7:0] rx_page_cnt /* synthesis noprune */;
+reg [7:0] rx_page_cnt;
 always @(negedge clk) begin
 	if(rx_new_page && !rx_new_pageD)
 		rx_page_cnt <= rx_page_cnt + 8'd1;
@@ -219,8 +219,6 @@ always @(posedge rx_write_clk or posedge rx_write_begin) begin
 			rx_w_cnt <= rx_w_cnt + 16'd1;
 			
 		end else if(rx_w_state == 2'd2) begin
-			// rx begin stays true over the entire transfer
-//			if(rx_begin)
 			rx_w_cnt <= rx_w_cnt + 16'd1;
 					
 		end else if(rx_w_state == 2'd3) begin
@@ -236,7 +234,7 @@ wire [7:0] header_byte =
 	(rx_w_cnt==1)?curr:
 	(rx_w_cnt==2)?rx_len[7:0]:
 	(rx_w_cnt==3)?rx_len[15:8]:
-	8'h55 /* synthesis keep*/ ;
+	8'h55;
 
 always @(posedge clk) begin
 	rx_lastByte <= 1'b0;
diff --git a/cores/mist/mist_top.v b/cores/mist/mist_top.v
index fae28b7..f503d81 100644
--- a/cores/mist/mist_top.v
+++ b/cores/mist/mist_top.v
@@ -747,16 +747,6 @@ always @ (posedge clk_32, negedge pll_locked) begin
 end
 
 assign clk_8 = clk_cnt[1];
-
-// bus cycle counter for debugging
-reg [31:0] cycle_counter /* synthesis noprune */;
-always @ (posedge clk_8) begin
-	if(reset)
-		cycle_counter <= 32'd0;
-	else
-		cycle_counter <= cycle_counter + 32'd1;
-end
-
  
 // tg68 bus interface. These are the signals which are latched
 // for the 8MHz bus.
diff --git a/cores/mist/ste_dma_snd.v b/cores/mist/ste_dma_snd.v
index cdb4e40..46b2115 100644
--- a/cores/mist/ste_dma_snd.v
+++ b/cores/mist/ste_dma_snd.v
@@ -52,7 +52,7 @@ module ste_dma_snd (
 // --------------------------- internal state counter ------------------------
 // ---------------------------------------------------------------------------
 
-reg [1:0] t /* synthesis noprune */ ;
+reg [1:0] t;
 always @(posedge clk32) begin
 	// 32Mhz counter synchronous to 8 Mhz clock
 	// force counter to pass state 0 exactly after the rising edge of clk (8Mhz)
@@ -254,7 +254,7 @@ reg [FIFO_ADDR_BITS-1:0] writeP, readP;
 wire fifo_empty = (readP == writeP);
 wire fifo_full = (readP == (writeP + 2'd1));
 
-reg [11:0] fifo_underflow /* synthesis noprune */;
+reg [11:0] fifo_underflow;
 
 // ---------------------------------------------------------------------------
 // -------------------------------- audio engine -----------------------------
@@ -294,7 +294,7 @@ always @(posedge aclk) begin
 			end else
 				// for debugging: monitor if fifo runs out of data
 				fifo_underflow <= fifo_underflow + 12'd1;
-		end
+		end 
 	end
 end
 
@@ -312,9 +312,8 @@ reg dma_enable;  // flag indicating dma engine is active
 // released for that event
 reg frame_done;
 assign xsint = dma_enable && (snd_adr != snd_end_latched);
-// assign xsint = dma_enable && !frame_done;
 
-reg [7:0] frame_cnt /* synthesis noprune */;
+reg [7:0] frame_cnt;
 
 always @(posedge clk32) begin
 	if(reset) begin