This chapter documents the Backend for the PowerPC microprocessor family.

@section Legal

    This module is written in 2002-2006,2008,2011 by Frank Wille.

    This archive may be redistributed without modifications and used
    for non-commercial purposes.

    Distributing modified versions and commercial usage needs my written
    consent.

    Certain modules may fall under additional copyrights.


@section Additional options for this module

This module provides the following additional options:

@table @option

    @item -big
        Select big-endian mode.

    @item -no-regnames
        Don't predefine any register-name symbols.

    @item -little
        Select little-endian mode.

    @item -mpwrx, -mpwr2
        Generate code for the POWER2 family.

    @item -mpwr
        Generate code for the POWER family.

    @item -m601
        Generate code for the 601.

    @item -mppc32, -mppc -m403, -m405, -m603, -m604, -m750, -m860
        Generate code for the 32-bit PowerPC family.

    @item -mppc64, -m620
        Generate code for the 64-bit PowerPC family.

    @item -mavec, -maltivec
        Generate code for the Altivec unit.

    @item -mcom
        Allow only common PPC instructions.

    @item -many
        Allow any PPC instruction.

    @item -sdreg=<n>
        Sets small data base register to @code{Rn}.

    @item -sd2reg=<n>
        Sets the 2nd small data base register to @code{Rn}.

    @item -opt-branch
        Enables 'optimization' of 16-bit branches into
        "B<!cc> $+8 ; B label" sequences when necessary.

@end table

@section General

This backend accepts PowerPC instructions as described in the
instruction set manuals from IBM and Motorola (e.g. the PowerPC
Programming Environments).

The full instruction set of the following families is supported:
POWER, POWER2, 40x, 60x, 620, 750, 74xx (including Altivec), 860.

The target address type is 32bit.

Default alignment for sections and instructions is 4 bytes. Data is
aligned to its natural alignment by default.

@section Extensions

This backend provides the following specific extensions:

@itemize @minus

@item When not disabled by the option @code{-no-regnames}, the registers r0 - r31,
 f0 - f31, v0 - v31, cr0 - cr7, vrsave, sp, rtoc, fp, fpscr, xer, lr, ctr,
 and the symbols lt, gt, so and un will be predefined on startup and may
 be referenced by the program.

@end itemize

This backend extends the selected syntax module by the following
directives:

@table @code
@item .sdreg <n>
 Sets the small data base register to @code{Rn}.

@item .sd2reg <n>
 Sets the 2nd small data base register to @code{Rn}.

@end table


@section Optimizations

This backend performs the following optimizations:

@itemize @minus

@item 16-bit branches, where the destination is out of range, are translated
 into @code{B<!cc> $+8} and a 26-bit unconditional branch.

@end itemize

@section Known Problems

    Some known problems of this module at the moment:

@itemize @minus

@item No real differantiation between 403, 750, 860 instructions
      at the moment.
@item New instructions from modern CPUs are still missing.

@end itemize

@section Error Messages

This module has the following error messages:

@itemize @minus
@item 2002: instruction not supported on selected architecture
@item 2003: constant integer expression required
@item 2004: trailing garbage in operand
@item 2005: illegal operand type
@item 2006: missing closing parenthesis in load/store addressing mode
@item 2007: relocation does not allow hi/lo modifier
@item 2008: multiple relocation attributes
@item 2009: multiple hi/lo modifiers
@item 2010: data size %d not supported
@item 2012: relocation attribute not supported by operand
@item 2013: operand out of range: %ld (allowed: %ld to %ld)
@item 2014: not a valid register (0-31)
@item 2015: missing base register in load/store addressing mode
@item 2016: missing mandatory operand
@item 2017: ignoring fake operand
@end itemize