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35 lines
593 B
Verilog
35 lines
593 B
Verilog
// A simple system-on-a-chip (SoC) for the MiST
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// (c) 2015 Till Harbaum
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module soc (
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input [1:0] CLOCK_27,
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output SDRAM_nCS,
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output VGA_HS,
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output VGA_VS,
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B
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);
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// de-activate unused SDRAM
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assign SDRAM_nCS = 1;
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wire pixel_clock;
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vga vga (
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.pclk (pixel_clock),
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.hs (VGA_HS),
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.vs (VGA_VS),
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.r (VGA_R),
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.g (VGA_G),
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.b (VGA_B)
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);
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// A PLL to derive the VGA pixel clocl from the MiSTs 27MHz
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pll pll (
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.inclk0(CLOCK_27[0]),
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.c0(pixel_clock) // 25.175 MHz
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);
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endmodule
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