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67 lines
1.4 KiB
Verilog
67 lines
1.4 KiB
Verilog
// A simple system-on-a-chip (SoC) for the MiST
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// (c) 2015 Till Harbaum
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module spi (
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input reset,
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input clk,
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// CPU interface
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input sel,
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input wr,
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input addr, // only 1 address bit required
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input [7:0] din,
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output [7:0] dout,
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// SPI/SD card interface
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output reg spi_ss,
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output reg spi_sck,
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output spi_sdo,
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input spi_sdi
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);
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// SPI SS bit is just a cpu controlled output port
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always @(negedge clk) begin
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if(reset)
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spi_ss <= 1'b1;
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else begin
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// ss is written on io addr 1
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if(sel && wr && addr)
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spi_ss <= din[0];
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end
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end
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// data is being sent with msb first
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assign spi_sdo = spi_tx_byte[7];
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reg [3:0] spi_state_cnt;
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reg [7:0] spi_tx_byte;
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reg [7:0] spi_rx_byte;
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always @(negedge clk) begin
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if(reset) begin
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spi_state_cnt <= 4'd0;
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spi_sck <= 1'b0;
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end else begin
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if(sel && wr && !addr) begin
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spi_state_cnt <= 4'd15;
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spi_tx_byte <= din;
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end else begin
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// rising spi clock on odd states
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spi_sck <= spi_state_cnt[0];
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// read input bit on rising clock edge, shift output bit on falling edge
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if(spi_state_cnt[0])
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spi_rx_byte <= { spi_rx_byte[6:0], spi_sdi };
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else
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spi_tx_byte <= { spi_tx_byte[6:0], 1'b0 };
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// decrease state counter
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if(spi_state_cnt != 0)
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spi_state_cnt <= spi_state_cnt - 4'd1;
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end
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end
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end
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assign dout = spi_rx_byte;
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endmodule
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