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86 lines
1.7 KiB
Verilog
86 lines
1.7 KiB
Verilog
// http://www.computer-engineering.org/ps2mouse/
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module mouse (
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input clk,
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input reset,
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// ps2 interface
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input ps2_clk,
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input ps2_data,
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// decodes keys
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output [7:0] x,
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input clr_x,
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output [7:0] y,
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input clr_y,
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output reg [1:0] b
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);
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assign x = x_pos[9:2];
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assign y = y_pos[9:2];
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reg [9:0] x_pos;
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reg [9:0] y_pos;
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wire [7:0] byte;
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wire valid;
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wire error;
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reg [1:0] cnt;
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reg sign_x, sign_y;
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reg [7:0] x_reg;
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always @(posedge clk) begin
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if(reset) begin
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x_pos <= 10'd0;
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y_pos <= 10'd0;
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cnt <= 2'd0;
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end else begin
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// ps2 decoder has received a valid byte
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if(valid) begin
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// count through all three data bytes
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cnt <= cnt + 2'd1;
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if(cnt == 0) begin
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// bit 3 must be 1. Stay in state 0 otherwise
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if(!byte[3]) cnt <= 2'd0;
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b <= byte[1:0];
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sign_x <= byte[4];
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sign_y <= byte[5];
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end else if(cnt == 1) begin
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x_reg <= byte;
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end else begin
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// the ps2 packet contains a 9 bit value. We only use the upper
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// 7. Otherwise the mouse would be too fast for our low resolution
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x_pos <= x_pos + { {2{sign_x}}, x_reg};
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y_pos <= y_pos + { {2{sign_y}}, byte};
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cnt <= 2'd0;
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end
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end
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// only the upper 8 bits of the 10 bit mouse position are reported byck to the
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// cpu
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if(clr_x) x_pos[9:2] <= 8'd0;
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if(clr_y) y_pos[9:2] <= 8'd0;
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end
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end
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// the ps2 decoder has been taken from the zx spectrum core
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ps2_intf ps2_keyboard (
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.CLK ( clk ),
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.nRESET ( !reset ),
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// PS/2 interface
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.PS2_CLK ( ps2_clk ),
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.PS2_DATA ( ps2_data ),
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// Byte-wide data interface - only valid for one clock
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// so must be latched externally if required
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.DATA ( byte ),
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.VALID ( valid ),
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.ERROR ( error )
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);
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endmodule
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