mirror of
https://github.com/mist-devel/mist-board.git
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403 lines
10 KiB
Verilog
403 lines
10 KiB
Verilog
//
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// user_io.v
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//
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// user_io for the MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// parameter STRLEN and the actual length of conf_str have to match
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module user_io #(parameter STRLEN=0) (
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input [(8*STRLEN)-1:0] conf_str,
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input SPI_SCK,
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input CONF_DATA0,
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output reg SPI_DO,
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input SPI_DI,
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output reg [7:0] joystick_0,
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output reg [7:0] joystick_1,
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output reg [15:0] joystick_analog_0,
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output reg [15:0] joystick_analog_1,
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output [1:0] buttons,
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output [1:0] switches,
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output scandoubler_disable,
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output reg [7:0] status,
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// connection to sd card emulation
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input [31:0] sd_lba,
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input sd_rd,
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input sd_wr,
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output reg sd_ack,
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input sd_conf,
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input sd_sdhc,
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output reg [7:0] sd_dout,
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output reg sd_dout_strobe,
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input [7:0] sd_din,
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output reg sd_din_strobe,
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output sd_mounted,
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// ps2 keyboard emulation
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input ps2_clk, // 12-16khz provided by core
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output ps2_kbd_clk,
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output reg ps2_kbd_data,
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output ps2_mouse_clk,
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output reg ps2_mouse_data,
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// serial com port
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input [7:0] serial_data,
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input serial_strobe
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);
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reg [6:0] sbuf;
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reg [7:0] cmd;
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reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
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reg [7:0] byte_cnt; // counts bytes
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reg [7:0] but_sw;
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reg [2:0] stick_idx;
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reg mount_strobe = 1'b0;
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assign sd_mounted = mount_strobe;
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assign buttons = but_sw[1:0];
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assign switches = but_sw[3:2];
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assign scandoubler_disable = but_sw[4];
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wire [7:0] dout = { sbuf, SPI_DI};
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// this variant of user_io is for 8 bit cores (type == a4) only
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wire [7:0] core_type = 8'ha4;
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// command byte read by the io controller
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wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
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// drive MISO only when transmitting core id
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always@(negedge SPI_SCK or posedge CONF_DATA0) begin
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if(CONF_DATA0 == 1) begin
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SPI_DO <= 1'bZ;
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end else begin
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// first byte returned is always core type, further bytes are
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// command dependent
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if(byte_cnt == 0) begin
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SPI_DO <= core_type[~bit_cnt];
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end else begin
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// reading serial fifo
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if(cmd == 8'h1b) begin
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// send alternating flag byte and data
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if(byte_cnt[0]) SPI_DO <= serial_out_status[~bit_cnt];
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else SPI_DO <= serial_out_byte[~bit_cnt];
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end
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// reading config string
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else if(cmd == 8'h14) begin
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// returning a byte from string
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if(byte_cnt < STRLEN + 1)
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SPI_DO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
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else
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SPI_DO <= 1'b0;
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end
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// reading sd card status
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else if(cmd == 8'h16) begin
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if(byte_cnt == 1)
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SPI_DO <= sd_cmd[~bit_cnt];
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else if((byte_cnt >= 2) && (byte_cnt < 6))
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SPI_DO <= sd_lba[{5-byte_cnt, ~bit_cnt}];
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else
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SPI_DO <= 1'b0;
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end
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// reading sd card write data
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else if(cmd == 8'h18)
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SPI_DO <= sd_din[~bit_cnt];
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else
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SPI_DO <= 1'b0;
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end
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end
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end
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// ---------------- PS2 ---------------------
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// 8 byte fifos to store ps2 bytes
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localparam PS2_FIFO_BITS = 3;
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// keyboard
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reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0];
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reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
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reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
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// ps2 transmitter state machine
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reg [3:0] ps2_kbd_tx_state;
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reg [7:0] ps2_kbd_tx_byte;
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reg ps2_kbd_parity;
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assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0);
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// ps2 transmitter
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// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
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reg ps2_kbd_r_inc;
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always@(posedge ps2_clk) begin
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ps2_kbd_r_inc <= 1'b0;
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if(ps2_kbd_r_inc)
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ps2_kbd_rptr <= ps2_kbd_rptr + 3'd1;
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// transmitter is idle?
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if(ps2_kbd_tx_state == 0) begin
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// data in fifo present?
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if(ps2_kbd_wptr != ps2_kbd_rptr) begin
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// load tx register from fifo
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ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
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ps2_kbd_r_inc <= 1'b1;
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// reset parity
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ps2_kbd_parity <= 1'b1;
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// start transmitter
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ps2_kbd_tx_state <= 4'd1;
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// put start bit on data line
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ps2_kbd_data <= 1'b0; // start bit is 0
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end
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end else begin
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// transmission of 8 data bits
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if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
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ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
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ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
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if(ps2_kbd_tx_byte[0])
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ps2_kbd_parity <= !ps2_kbd_parity;
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end
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// transmission of parity
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if(ps2_kbd_tx_state == 9)
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ps2_kbd_data <= ps2_kbd_parity;
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// transmission of stop bit
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if(ps2_kbd_tx_state == 10)
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ps2_kbd_data <= 1'b1; // stop bit is 1
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// advance state machine
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if(ps2_kbd_tx_state < 11)
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ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1;
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else
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ps2_kbd_tx_state <= 4'd0;
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end
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end
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// mouse
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reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0];
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reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
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reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
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// ps2 transmitter state machine
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reg [3:0] ps2_mouse_tx_state;
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reg [7:0] ps2_mouse_tx_byte;
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reg ps2_mouse_parity;
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assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0);
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// ps2 transmitter
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// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
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reg ps2_mouse_r_inc;
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always@(posedge ps2_clk) begin
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ps2_mouse_r_inc <= 1'b0;
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if(ps2_mouse_r_inc)
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ps2_mouse_rptr <= ps2_mouse_rptr + 3'd1;
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// transmitter is idle?
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if(ps2_mouse_tx_state == 0) begin
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// data in fifo present?
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if(ps2_mouse_wptr != ps2_mouse_rptr) begin
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// load tx register from fifo
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ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
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ps2_mouse_r_inc <= 1'b1;
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// reset parity
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ps2_mouse_parity <= 1'b1;
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// start transmitter
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ps2_mouse_tx_state <= 4'd1;
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// put start bit on data line
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ps2_mouse_data <= 1'b0; // start bit is 0
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end
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end else begin
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// transmission of 8 data bits
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if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
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ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
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ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
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if(ps2_mouse_tx_byte[0])
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ps2_mouse_parity <= !ps2_mouse_parity;
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end
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// transmission of parity
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if(ps2_mouse_tx_state == 9)
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ps2_mouse_data <= ps2_mouse_parity;
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// transmission of stop bit
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if(ps2_mouse_tx_state == 10)
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ps2_mouse_data <= 1'b1; // stop bit is 1
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// advance state machine
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if(ps2_mouse_tx_state < 11)
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ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1;
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else
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ps2_mouse_tx_state <= 4'd0;
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end
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end
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// fifo to receive serial data from core to be forwarded to io controller
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// 16 byte fifo to store serial bytes
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localparam SERIAL_OUT_FIFO_BITS = 6;
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reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0];
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reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr;
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reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr;
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wire serial_out_data_available = serial_out_wptr != serial_out_rptr;
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wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */;
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wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available};
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// status[0] is reset signal from io controller and is thus used to flush
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// the fifo
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always @(posedge serial_strobe or posedge status[0]) begin
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if(status[0] == 1) begin
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serial_out_wptr <= 0;
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end else begin
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serial_out_fifo[serial_out_wptr] <= serial_data;
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serial_out_wptr <= serial_out_wptr + 6'd1;
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end
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end
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always@(negedge SPI_SCK or posedge status[0]) begin
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if(status[0] == 1) begin
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serial_out_rptr <= 0;
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end else begin
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if((byte_cnt != 0) && (cmd == 8'h1b)) begin
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// read last bit -> advance read pointer
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if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available)
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serial_out_rptr <= serial_out_rptr + 6'd1;
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end
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end
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end
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// SPI receiver
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always@(posedge SPI_SCK or posedge CONF_DATA0) begin
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if(CONF_DATA0 == 1) begin
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bit_cnt <= 3'd0;
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byte_cnt <= 8'd0;
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sd_ack <= 1'b0;
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sd_dout_strobe <= 1'b0;
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sd_din_strobe <= 1'b0;
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end else begin
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sd_dout_strobe <= 1'b0;
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sd_din_strobe <= 1'b0;
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sbuf <= dout[6:0];
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bit_cnt <= bit_cnt + 3'd1;
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// finished reading command byte
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if(bit_cnt == 7) begin
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if(byte_cnt != 8'd255) byte_cnt <= byte_cnt + 8'd1;
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if(byte_cnt == 0) begin
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cmd <= dout;
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// fetch first byte when sectore FPGA->IO command has been seen
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if(dout == 8'h18)
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sd_din_strobe <= 1'b1;
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if((dout == 8'h17) || (dout == 8'h18))
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sd_ack <= 1'b1;
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mount_strobe <= 1'b0;
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end else begin
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case(cmd)
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// buttons and switches
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8'h01: but_sw <= dout;
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8'h02: joystick_0 <= dout;
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8'h03: joystick_1 <= dout;
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// store incoming ps2 mouse bytes
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8'h04: begin
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ps2_mouse_fifo[ps2_mouse_wptr] <= dout;
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ps2_mouse_wptr <= ps2_mouse_wptr + 3'd1;
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end
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// store incoming ps2 keyboard bytes
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8'h05: begin
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ps2_kbd_fifo[ps2_kbd_wptr] <= dout;
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ps2_kbd_wptr <= ps2_kbd_wptr + 3'd1;
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end
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8'h15: status <= dout;
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// send SD config IO -> FPGA
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// flag that download begins
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// sd card knows data is config if sd_dout_strobe is asserted
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// with sd_ack still being inactive (low)
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8'h19,
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// send sector IO -> FPGA
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// flag that download begins
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8'h17: begin
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sd_dout <= dout;
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sd_dout_strobe <= 1'b1;
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end
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// send sector FPGA -> IO
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8'h18: sd_din_strobe <= 1'b1;
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// joystick analog
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8'h1a: begin
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// first byte is joystick index
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if(byte_cnt == 1) stick_idx <= dout[2:0];
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else if(byte_cnt == 2) begin
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// second byte is x axis
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if(stick_idx == 0) joystick_analog_0[15:8] <= dout;
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else if(stick_idx == 1) joystick_analog_1[15:8] <= dout;
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end else if(byte_cnt == 3) begin
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// third byte is y axis
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if(stick_idx == 0) joystick_analog_0[7:0] <= dout;
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else if(stick_idx == 1) joystick_analog_1[7:0] <= dout;
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end
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end
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// notify image selection
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8'h1c: mount_strobe <= 1'b1;
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default: ;
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endcase
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end
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end
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end
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end
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endmodule
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