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56 lines
1.4 KiB
Verilog
56 lines
1.4 KiB
Verilog
//
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// mste_ctrl.v
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//
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// Atari Mega STE cache/cpu controller implementation for the MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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module mste_ctrl (
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// cpu register interface
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input clk,
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input reset,
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input [7:0] din,
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input sel,
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input ds,
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input rw,
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output reg [7:0] dout,
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output enable_cache,
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output enable_16mhz
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);
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assign enable_16mhz = mste_config[0];
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assign enable_cache = mste_config[1];
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reg [7:0] mste_config;
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always @(sel, ds, rw, mste_config) begin
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dout = 8'd0;
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if(sel && ~ds && rw)
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dout = mste_config;
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end
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always @(negedge clk) begin
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if(reset)
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mste_config <= 8'h00;
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else begin
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if(sel && ~ds && ~rw)
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mste_config <= din;
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end
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end
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endmodule |