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74 lines
1.5 KiB
Verilog
74 lines
1.5 KiB
Verilog
// A simple system-on-a-chip (SoC) for the MiST
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// (c) 2015 Till Harbaum
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module soc (
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input [1:0] CLOCK_27,
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output SDRAM_nCS,
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output VGA_HS,
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output VGA_VS,
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B
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);
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// de-activate unused SDRAM
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assign SDRAM_nCS = 1;
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wire pixel_clock;
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// include VGA controller
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vga vga (
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.pclk (pixel_clock),
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.cpu_clk ( pixel_clock ),
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.cpu_wr ( copy_in_progress ),
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.cpu_addr ( addr - 14'd1 ),
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.cpu_data ( data ),
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.hs (VGA_HS),
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.vs (VGA_VS),
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.r (VGA_R),
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.g (VGA_G),
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.b (VGA_B)
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);
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// include ROM containing the demo image
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image image (
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.clock ( pixel_clock ),
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.address ( addr ),
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.q ( data )
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);
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reg reset = 1'b1;
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reg [13:0] addr;
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wire [7:0] data;
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reg copy_in_progress;
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// A small state machine which copies image data from ROM into VRAM
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// of the video controller. The state machines runs directly after power
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// on and works on the falling clock edge since ROM and VRAM operate
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// in the rising edge. The VRAM address is dereased by 1 since the ROM
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// delivers it's data with one clock delay due to its internal registers.
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always @(negedge pixel_clock) begin
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if(reset) begin
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reset <= 1'b0;
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addr <= 14'd0;
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copy_in_progress <= 1'b1;
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end else begin
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if(copy_in_progress) begin
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addr <= addr + 14'd1;
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if(addr == 15999)
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copy_in_progress <= 1'b0;
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end
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end
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end
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// A PLL to derive the VGA pixel clocl from the MiSTs 27MHz
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pll pll (
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.inclk0(CLOCK_27[0]),
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.c0(pixel_clock) // 25.175 MHz
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);
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endmodule
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