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154 lines
4.7 KiB
Verilog
154 lines
4.7 KiB
Verilog
//
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// cache.v
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//
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// Atari ST CPU cache implementation for the MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module cache (
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input clk_128,
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input clk,
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input reset,
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input flush,
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input strobe,
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input [22:0] addr, // cpu word address
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input [1:0] ds, // upper (0) and lower (1) data strobe
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output [15:0] dout,
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output hit,
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// interface to store entire cache lines when read from ram
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input [63:0] din64,
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input store,
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// interface to update existing cache lines on cpu ram write
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input [15:0] din16,
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input update
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);
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// cache size configuration
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// the cache size in bytes is 8*(2^BITS), e.g. 2kBytes if BITS == 8
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localparam BITS = 8;
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// _word_ address mapping example with 16 cache lines (BITS == 4)
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// 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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// T T T T T T T T T T T T T L L L L L L L L W W
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// T = stored in tag RAM
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// L = cache line
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// W = 16 bit word select
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wire [21-BITS-1:0] tag = addr[22:2+BITS];
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wire [BITS-1:0] line = addr[2+BITS-1:2];
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/* ------------------------------------------------------------------------------ */
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/* --------------------------------- cache memory ------------------------------- */
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/* ------------------------------------------------------------------------------ */
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// 8 bytes wide storage
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parameter ENTRIES = 2 ** BITS;
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reg [7:0] data_latch_7 [ENTRIES-1:0];
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reg [7:0] data_latch_6 [ENTRIES-1:0];
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reg [7:0] data_latch_5 [ENTRIES-1:0];
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reg [7:0] data_latch_4 [ENTRIES-1:0];
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reg [7:0] data_latch_3 [ENTRIES-1:0];
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reg [7:0] data_latch_2 [ENTRIES-1:0];
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reg [7:0] data_latch_1 [ENTRIES-1:0];
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reg [7:0] data_latch_0 [ENTRIES-1:0];
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reg [21-BITS-1:0] tag_latch [ENTRIES-1:0];
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reg [ENTRIES-1:0] valid;
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reg [21-BITS-1:0] current_tag;
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// signal indicating the currently selected cache line is valid and matches the
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// address the cpu is currently requesting
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// assign hit = valid[line] && (tag_latch[line] == tag);
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assign hit = valid[line] && (current_tag == tag);
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reg [15:0] dout_latch_0;
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reg [15:0] dout_latch_1;
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reg [15:0] dout_latch_2;
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reg [15:0] dout_latch_3;
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// permanently output data according to current line
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// de-multiplex 64 bit data into word requested by cpu
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assign dout = (addr[1:0] == 0)?dout_latch_0:
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(addr[1:0] == 1)?dout_latch_1:
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(addr[1:0] == 2)?dout_latch_2:
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dout_latch_3;
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always @(posedge clk_128) begin
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dout_latch_0 <= {data_latch_1[line], data_latch_0[line]};
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dout_latch_1 <= {data_latch_3[line], data_latch_2[line]};
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dout_latch_2 <= {data_latch_5[line], data_latch_4[line]};
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dout_latch_3 <= {data_latch_7[line], data_latch_6[line]};
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current_tag <= tag_latch[line];
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end
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wire clear = reset || flush;
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always @(posedge clk or posedge clear) begin
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if(clear) begin
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valid <= { ENTRIES {1'b0} };
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end else begin
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// store indicates that a whole cache line is to be stored
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if(store) begin
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data_latch_7[line] <= din64[63:56];
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data_latch_6[line] <= din64[55:48];
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data_latch_5[line] <= din64[47:40];
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data_latch_4[line] <= din64[39:32];
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data_latch_3[line] <= din64[31:24];
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data_latch_2[line] <= din64[23:16];
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data_latch_1[line] <= din64[15: 8];
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data_latch_0[line] <= din64[ 7: 0];
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tag_latch[line] <= tag;
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valid[line] <= 1'b1;
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end
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// cpu (or other bus master!) writes to ram, so update cache contents if necessary
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else if(update && hit) begin
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// no need to care for "tag_latch" or "valid" as they simply stay the same
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case(addr[1:0])
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0: begin
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if(ds[1]) data_latch_0[line] <= din16[7:0];
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if(ds[0]) data_latch_1[line] <= din16[15:8];
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end
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1: begin
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if(ds[1]) data_latch_2[line] <= din16[7:0];
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if(ds[0]) data_latch_3[line] <= din16[15:8];
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end
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2: begin
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if(ds[1]) data_latch_4[line] <= din16[7:0];
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if(ds[0]) data_latch_5[line] <= din16[15:8];
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end
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3: begin
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if(ds[1]) data_latch_6[line] <= din16[7:0];
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if(ds[0]) data_latch_7[line] <= din16[15:8];
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end
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endcase
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end
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end
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end
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endmodule
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