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97 lines
3.5 KiB
VHDL
Executable File
97 lines
3.5 KiB
VHDL
Executable File
-- ZX Spectrum for Altera DE1
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--
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-- Copyright (c) 2009-2011 Mike Stirling
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- * Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- * Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- * Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written agreement from the author.
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--
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-- * License is granted for non-commercial use only. A fee may not be charged
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-- for redistributions as source code or in synthesized/hardware form without
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-- specific prior written agreement from the author.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity clocks is
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port (
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-- 28 MHz master clock
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CLK : in std_logic;
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-- Master reset
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nRESET : in std_logic;
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-- cpu requests bus
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MREQ : in std_logic;
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-- 1.75 MHz clock enable for sound
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CLKEN_PSG : out std_logic;
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-- 3.5 MHz clock enable (1 in 8)
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CLKEN_CPU : out std_logic;
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-- 3.5 MHz clock enable (1 in 8) for cpu memory access
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CLKEN_MEM : out std_logic;
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-- 1.75 MHz clock enable (1 in 8) for data_io
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CLKEN_DIO : out std_logic;
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-- 14 MHz clock enable (out of phase with CPU)
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CLKEN_VID : out std_logic
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);
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end clocks;
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-- Clock enables for uncontended VRAM access
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-- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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-- CPU VID VID VID VID CPU VID VID VID VID
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-- DIO MEM PSG
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architecture clocks_arch of clocks is
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signal counter : unsigned(3 downto 0);
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signal mreq_D : std_logic;
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begin
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-- X000
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-- CPU may used 1000 state only if it doesn't use the memory bus
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CLKEN_CPU <= '1' when (counter = "1000" and mreq_D = '0')
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or counter = "0000" else '0';
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-- 1000
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CLKEN_DIO <= '1' when counter = "1101" else '0';
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-- 1001
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CLKEN_MEM <= '1' when counter = "1001" else '0';
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-- XXX1
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CLKEN_VID <= '1' when counter(0) = '1' else '0';
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-- 1111
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CLKEN_PSG <= '1' when counter = "1111" else '0';
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process(nRESET,CLK)
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begin
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if nRESET = '0' then
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counter <= (others => '0');
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elsif falling_edge(CLK) then
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counter <= counter + 1;
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mreq_D <= MREQ;
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end if;
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end process;
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end clocks_arch;
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