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143 lines
3.9 KiB
Verilog
143 lines
3.9 KiB
Verilog
// A simple system-on-a-chip (SoC) for the MiST
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// (c) 2015 Till Harbaum
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module soc (
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input [1:0] CLOCK_27,
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// SDRAM interface
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inout [15:0] SDRAM_DQ, // SDRAM Data bus 16 Bits
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output [12:0] SDRAM_A, // SDRAM Address bus 13 Bits
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output SDRAM_DQML, // SDRAM Low-byte Data Mask
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output SDRAM_DQMH, // SDRAM High-byte Data Mask
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output SDRAM_nWE, // SDRAM Write Enable
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output SDRAM_nCAS, // SDRAM Column Address Strobe
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output SDRAM_nRAS, // SDRAM Row Address Strobe
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output SDRAM_nCS, // SDRAM Chip Select
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output [1:0] SDRAM_BA, // SDRAM Bank Address
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output SDRAM_CLK, // SDRAM Clock
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output SDRAM_CKE, // SDRAM Clock Enable
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// VGA interface
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output VGA_HS,
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output VGA_VS,
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B
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);
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wire pixel_clock;
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// include VGA controller
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vga vga (
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.pclk ( pixel_clock ),
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.cpu_clk ( cpu_clock ),
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.cpu_wr ( !cpu_wr_n && !cpu_addr[15] ),
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.cpu_addr ( cpu_addr[13:0] ),
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.cpu_data ( cpu_dout ),
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.hs (VGA_HS),
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.vs (VGA_VS),
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.r (VGA_R),
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.g (VGA_G),
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.b (VGA_B)
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);
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// The CPU is kept in reset for further 256 cyckes after the PLL is
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// generating stable clocks to make sure things like the SDRAM have
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// some time to initialize
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reg [7:0] cpu_reset_cnt = 8'h00;
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wire cpu_reset = (cpu_reset_cnt != 255);
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always @(posedge cpu_clock) begin
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if(!pll_locked)
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cpu_reset_cnt <= 8'd0;
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else
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if(cpu_reset_cnt != 255)
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cpu_reset_cnt <= cpu_reset_cnt + 8'd1;
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end
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// SDRAM control signals
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wire ram_clock;
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assign SDRAM_CKE = 1'b1;
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sdram sdram (
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// interface to the MT48LC16M16 chip
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.sd_data ( SDRAM_DQ ),
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.sd_addr ( SDRAM_A ),
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.sd_dqm ( {SDRAM_DQMH, SDRAM_DQML} ),
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.sd_cs ( SDRAM_nCS ),
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.sd_ba ( SDRAM_BA ),
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.sd_we ( SDRAM_nWE ),
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.sd_ras ( SDRAM_nRAS ),
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.sd_cas ( SDRAM_nCAS ),
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// system interface
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.clk ( ram_clock ),
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.clkref ( cpu_clock ),
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.init ( !pll_locked ),
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// cpu/chipset interface
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.din ( cpu_dout ),
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.addr ( { 10'd0, cpu_addr[14:0] } ),
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.we ( !cpu_wr_n && cpu_addr[15] ),
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.oe ( !cpu_rd_n && cpu_addr[15] ),
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.dout ( ram_data_out )
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);
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// CPU control signals
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wire cpu_clock;
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wire [15:0] cpu_addr;
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wire [7:0] cpu_din;
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wire [7:0] cpu_dout;
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wire cpu_rd_n;
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wire cpu_wr_n;
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wire cpu_mreq_n;
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// include Z80 CPU
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T80s T80s (
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.RESET_n ( !cpu_reset ),
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.CLK_n ( cpu_clock ),
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.WAIT_n ( 1'b1 ),
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.INT_n ( 1'b1 ),
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.NMI_n ( 1'b1 ),
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.BUSRQ_n ( 1'b1 ),
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.MREQ_n ( cpu_mreq_n ),
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.RD_n ( cpu_rd_n ),
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.WR_n ( cpu_wr_n ),
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.A ( cpu_addr ),
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.DI ( cpu_din ),
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.DO ( cpu_dout )
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);
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// map 32k SDRAM into upper half od the address space (A15=1)
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// and 4k ROM into the lower half (A15=0)
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wire [7:0] ram_data_out, rom_data_out;
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assign cpu_din = cpu_addr[15]?ram_data_out:rom_data_out;
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// include 4k program code from boot_rom
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boot_rom boot_rom (
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.clock ( cpu_clock ),
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.address ( cpu_addr[11:0] ),
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.q ( rom_data_out )
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);
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// derive 4Mhz cpu clock from 32Mhz sdram clock
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assign cpu_clock = clk_div[2];
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reg [2:0] clk_div;
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always @(posedge ram_clock)
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clk_div <= clk_div + 3'd1;
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// PLL to generate 32Mhz ram clock and 25Mhz video clock from MiSTs
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// 27Mhz on board clock
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wire pll_locked;
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pll pll (
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.inclk0 ( CLOCK_27[0] ),
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.locked ( pll_locked ), // PLL is running stable
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.c0 ( pixel_clock ), // 25.175 MHz
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.c1 ( ram_clock ), // 32 MHz
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.c2 ( SDRAM_CLK ) // slightly phase shifted 32 MHz
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);
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endmodule
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