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223 lines
8.1 KiB
Verilog
223 lines
8.1 KiB
Verilog
module addrController_top(
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// clocks:
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input clk8, // 8.125 MHz CPU clock
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// system config:
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input configROMSize, // 0 = 64K ROM, 1 = 128K ROM
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input [1:0] configRAMSize, // 0 = 128K, 1 = 512K, 2 = 1MB, 3 = 4MB RAM
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// 68000 CPU memory interface:
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input [23:0] cpuAddr,
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input _cpuAS,
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input _cpuUDS,
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input _cpuLDS,
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input _cpuRW,
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output _cpuDTACK,
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// RAM/ROM:
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output [21:0] memoryAddr,
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output _memoryUDS,
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output _memoryLDS,
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output _romOE,
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output _ramOE,
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output _ramWE,
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output videoBusControl,
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output dioBusControl,
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// peripherals:
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output selectSCC,
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output selectIWM,
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output selectVIA,
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// video:
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output hsync,
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output vsync,
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output _hblank,
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output _vblank,
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output loadPixels,
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input snd_alt,
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output loadSound,
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// misc
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input memoryOverlayOn,
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// interface to read dsk image from ram
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input [21:0] dskReadAddrInt,
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output dskReadAckInt,
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input [21:0] dskReadAddrExt,
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output dskReadAckExt
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);
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// -------------- audio engine (may be moved into seperate module) ---------------
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assign loadSound = sndReadAck;
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localparam SIZE = 20'd67704; // 168*608/2 clk8 events per frame
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localparam STEP = 20'd5920; // one step every 16*370 clk8 events
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reg [21:0] audioAddr;
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reg [19:0] snd_div;
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reg sndReadAckD;
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always @(negedge clk8)
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sndReadAckD <= sndReadAck;
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reg vblankD, vblankD2;
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always @(posedge clk8) begin
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if(sndReadAckD) begin
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vblankD <= _vblank;
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vblankD2 <= vblankD;
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// falling adge of _vblank = begin of vblank phase
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if(vblankD2 && !vblankD) begin
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audioAddr <= snd_alt?22'h3FA100:22'h3FFD00;
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snd_div <= 20'd0;
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end else begin
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if(snd_div >= SIZE-1) begin
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snd_div <= snd_div - SIZE + STEP;
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audioAddr <= audioAddr + 22'd2;
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end else
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snd_div <= snd_div + STEP;
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end
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end
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end
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assign dioBusControl = extraBusControl;
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// interleaved RAM access for CPU and video
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reg [1:0] busCycle;
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always @(posedge clk8)
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busCycle <= busCycle + 2'd1;
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// video controls memory bus during the first clock of the four-clock cycle
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assign videoBusControl = (busCycle == 2'b00);
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// cpu controls memory bus during the third clock of the four-clock cycle
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wire cpuBusControl = (busCycle == 2'b10);
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//
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wire extraBusControl = (busCycle == 2'b01);
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// DTACK generation
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// TODO: delay DTACK for once full bus cycle when RAM is accessed, to match Mac Plus memory timing
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// TODO: according to datasheet, /DTACK should continue to be asserted through the final bus cycle too
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assign _cpuDTACK = ~(_cpuAS == 1'b0 && cpuBusControl);
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// interconnects
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wire selectRAM, selectROM;
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wire [21:0] videoAddr;
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// RAM/ROM control signals
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wire videoControlActive = _hblank;
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wire extraRomRead = dskReadAckInt || dskReadAckExt;
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assign _romOE = ~(extraRomRead || (cpuBusControl && selectROM == 1'b1 && _cpuRW == 1'b1));
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wire extraRamRead = sndReadAck;
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assign _ramOE = ~((videoBusControl && videoControlActive == 1'b1) || (extraRamRead) ||
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(cpuBusControl && selectRAM == 1'b1 && _cpuRW == 1'b1));
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assign _ramWE = ~(cpuBusControl && selectRAM && _cpuRW == 1'b0);
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assign _memoryUDS = cpuBusControl ? _cpuUDS : 1'b0;
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assign _memoryLDS = cpuBusControl ? _cpuLDS : 1'b0;
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wire [21:0] addrMux = sndReadAck ? audioAddr : videoBusControl ? videoAddr : cpuAddr[21:0];
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wire [21:0] macAddr;
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assign macAddr[15:0] = addrMux[15:0];
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// video and sound always addresses ram
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wire ram_access = (cpuBusControl && selectRAM) || videoBusControl || sndReadAck;
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wire rom_access = (cpuBusControl && selectROM);
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// simulate smaller RAM/ROM sizes
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assign macAddr[16] = rom_access && configROMSize == 1'b0 ? 1'b0 : // force A16 to 0 for 64K ROM access
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addrMux[16];
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assign macAddr[17] = ram_access && configRAMSize == 2'b00 ? 1'b0 : // force A17 to 0 for 128K RAM access
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rom_access && configROMSize == 1'b1 ? 1'b0 : // force A17 to 0 for 128K ROM access
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rom_access && configROMSize == 1'b0 ? 1'b1 : // force A17 to 1 for 64K ROM access (64K ROM image is at $20000)
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addrMux[17];
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assign macAddr[18] = ram_access && configRAMSize == 2'b00 ? 1'b0 : // force A18 to 0 for 128K RAM access
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rom_access ? 1'b0 : // force A18 to 0 for ROM access
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addrMux[18];
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assign macAddr[19] = ram_access && configRAMSize[1] == 1'b0 ? 1'b0 : // force A19 to 0 for 128K or 512K RAM access
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rom_access ? 1'b0 : // force A19 to 0 for ROM access
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addrMux[19];
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assign macAddr[20] = ram_access && configRAMSize != 2'b11 ? 1'b0 : // force A20 to 0 for all but 4MB RAM access
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rom_access ? 1'b0 : // force A20 to 0 for ROM access
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addrMux[20];
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assign macAddr[21] = ram_access && configRAMSize != 2'b11 ? 1'b0 : // force A21 to 0 for all but 4MB RAM access
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rom_access ? 1'b0 : // force A21 to 0 for ROM access
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addrMux[21];
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// allocate memory slots in the extra cycle
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reg [2:0] extra_slot_count;
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always @(posedge clk8)
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if(busCycle == 2'b11)
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extra_slot_count <= extra_slot_count + 2'd1;
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// floppy emulation gets extra slots 0 and 1
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assign dskReadAckInt = (extraBusControl == 1'b1) && (extra_slot_count == 0);
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assign dskReadAckExt = (extraBusControl == 1'b1) && (extra_slot_count == 1);
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// audio gets extra slot 2
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assign sndReadAck = (extraBusControl == 1'b1) && (extra_slot_count == 2);
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assign memoryAddr =
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dskReadAckInt ? dskReadAddrInt + 22'h100000: // first dsk image at 1MB
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dskReadAckExt ? dskReadAddrExt + 22'h200000: // second dsk image at 2MB
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macAddr;
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// address decoding
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wire selectSCCByAddress;
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wire selectIWMByAddress;
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wire selectVIAByAddress;
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addrDecoder ad(
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.address(cpuAddr),
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.enable(!videoBusControl),
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._cpuAS(_cpuAS),
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.memoryOverlayOn(memoryOverlayOn),
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.selectRAM(selectRAM),
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.selectROM(selectROM),
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.selectSCC(selectSCCByAddress),
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.selectIWM(selectIWMByAddress),
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.selectVIA(selectVIAByAddress));
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/* TH: The following isn't 100% true anymore but kept for now for documentation purposes ...
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SCC register access is a mess. Reads and writes can have side-effects that alter the meaning of subsequent reads
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and writes to the same address. It's not safe to do multiple reads of the same address, or multiple writes of the
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same value to the same address. So we need to be sure we only perform one read or write per 4-clock CPU bus cycle.
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To complicate things, the CPU latches read data half-way through the last clock of the cycle, then deasserts the
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address, address strobe, and data for the remainder of the cycle (although RW remains valid). This behavior may
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be specified to TG68 and not shared by the real 68000.
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For writes to the SCC, we enable SCC only on clock 2, to guarantee one write per bus cycle.
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For reads, it's more difficult. If we enable SCC only on clock 2, then it won't be enabled during clock 3 when the
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CPU latches the data, so the read will fail. If we enable it only on clock 3, then the AS won't be asserted all
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the way to the end of the clock, so the read side-effect will fail. If we enable it on clock 2 and 3, then the
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CPU will read the post-side-effect value instead of the pre-side-effect value.
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The solution used here is to enable reads on clock 2 (when the side-effect is performed), and for the first half
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of clock 3, and to apply a one cycle delay to CPU data reads from the SCC. Reads only enable for the first half
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of clock 3 in case a later 68000 variant continues to assert AS all the way to the end of the clock, to ensure
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side-effects are not applied again.
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Another solution would be to create a custom clock for the SCC, whose positive edge is the negative edge of
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clock 3 of the bus cycle.
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*/
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assign selectSCC = selectSCCByAddress && cpuBusControl;
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assign selectIWM = selectIWMByAddress && cpuBusControl;
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assign selectVIA = selectVIAByAddress && cpuBusControl;
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// video
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videoTimer vt(
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.clk8(clk8),
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.busCycle(busCycle),
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.videoAddr(videoAddr),
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.hsync(hsync),
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.vsync(vsync),
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._hblank(_hblank),
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._vblank(_vblank),
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.loadPixels(loadPixels));
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endmodule
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