Gyorgy Szombathelyi c8d2bb5c00 [Archie] Use only one clock in the FDC

2019-02-24 00:21:28 +01:00

..

amber

Adding the achie source code.

2016-05-23 17:05:43 +01:00

i2cslave

Adding the achie source code.

2016-05-23 17:05:43 +01:00

sdram

[Archie] Improve SDRAM controller

2019-02-14 20:55:53 +01:00

archimedes_top.v

[Archie] Use only one clock in vidc (port from MiSTer)

2019-02-08 12:32:34 +01:00

blockram.v

removed the unused uart.

2016-05-23 20:23:21 +01:00

fdc1772.v

[Archie] Use only one clock in the FDC

2019-02-24 00:21:28 +01:00

floppy.v

[Archie] Use only one clock in the FDC

2019-02-24 00:21:28 +01:00

ioc_irq.v

Adding the achie source code.

2016-05-23 17:05:43 +01:00

ioc.v

[Archie] Use only clk_32 in user_io and ioc

2019-02-09 00:18:36 +01:00

latches.v

removed the unused uart.

2016-05-23 20:23:21 +01:00

memc_translator.v

Adding the achie source code.

2016-05-23 17:05:43 +01:00

memc.v

removed the unused uart.

2016-05-23 20:23:21 +01:00

podules.v

removed the unused uart.

2016-05-23 20:23:21 +01:00

por.v

removed the unused uart.

2016-05-23 20:23:21 +01:00

vidc_audio.v

[Archie] Use only one clock in vidc (port from MiSTer)

2019-02-08 12:32:34 +01:00

vidc_divider.v

Adding the achie source code.

2016-05-23 17:05:43 +01:00

vidc_dmachannel.v

[Archie] Use only one clock in vidc (port from MiSTer)

2019-02-08 12:32:34 +01:00

vidc_fifo.v

[Archie] Use only one clock in vidc (port from MiSTer)

2019-02-08 12:32:34 +01:00

vidc_mulaw.mif

Adding the achie source code.

2016-05-23 17:05:43 +01:00

vidc_timing.v

[Archie] Use only one clock in vidc (port from MiSTer)

2019-02-08 12:32:34 +01:00

vidc.v

[Archie] Use only one clock in vidc (port from MiSTer)

2019-02-08 12:32:34 +01:00