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120 lines
3.1 KiB
Verilog
120 lines
3.1 KiB
Verilog
//
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// data_io.v
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//
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// io controller writable ram for the MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module data_io #(parameter ADDR_WIDTH=16, START_ADDR = 0) (
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// io controller spi interface
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input sck,
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input ss,
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input sdi,
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output downloading, // signal indicating an active download
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output [ADDR_WIDTH-1:0] size, // number of bytes in input buffer
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// external ram interface
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input clk,
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output reg wr,
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output reg [ADDR_WIDTH-1:0] a,
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output [7:0] d
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);
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assign d = data;
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assign size = addr - START_ADDR;
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// *********************************************************************************
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// spi client
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// *********************************************************************************
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// this core supports only the display related OSD commands
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// of the minimig
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reg [6:0] sbuf;
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reg [7:0] cmd;
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reg [7:0] data;
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reg [4:0] cnt;
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reg [ADDR_WIDTH-1:0] addr;
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reg rclk;
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localparam UIO_FILE_TX = 8'h53;
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localparam UIO_FILE_TX_DAT = 8'h54;
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assign downloading = downloading_reg;
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reg downloading_reg = 1'b0;
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// filter spi clock. the 8 bit gate delay is ~2.5ns in total
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wire [7:0] spi_sck_D = { spi_sck_D[6:0], sck } /* synthesis keep */;
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wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
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// data_io has its own SPI interface to the io controller
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always@(posedge spi_sck, posedge ss) begin
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if(ss == 1'b1)
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cnt <= 5'd0;
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else begin
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rclk <= 1'b0;
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// don't shift in last bit. It is evaluated directly
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// when writing to ram
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if(cnt != 15)
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sbuf <= { sbuf[5:0], sdi};
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// increase target address after write
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if(rclk)
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addr <= addr + 1;
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// count 0-7 8-15 8-15 ...
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if(cnt < 15) cnt <= cnt + 4'd1;
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else cnt <= 4'd8;
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// finished command byte
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if(cnt == 7)
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cmd <= {sbuf, sdi};
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// prepare/end transmission
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if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
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// prepare
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if(sdi) begin
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addr <= START_ADDR;
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downloading_reg <= 1'b1;
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end else
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downloading_reg <= 1'b0;
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end
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// command 0x54: UIO_FILE_TX
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if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
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data <= {sbuf, sdi};
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rclk <= 1'b1;
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a <= addr;
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end
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end
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end
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reg rclkD, rclkD2;
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always@(posedge clk) begin
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// bring rclk from spi clock domain into c64 clock domain
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rclkD <= rclk;
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rclkD2 <= rclkD;
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wr <= 1'b0;
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if(rclkD && !rclkD2)
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wr <= 1'b1;
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end
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endmodule |