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70 lines
1.9 KiB
Verilog
70 lines
1.9 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Copyright 2013-2016 Istvan Hegedus
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//
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// FPGATED is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// FPGATED is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Create Date: 22:20:09 12/09/2014
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// Module Name: basic_rom.v
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// Project Name: FPGATED
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// Target Devices: Xilinx Spartan 3E
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//
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// Description:
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// Basic ROM synthetised to FPGA's internal SRAM. Xilinx ISE requires
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// ROM_STYLE="BLOCK" parameter next to kernal array. For other vendor's
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// device syntax refer to the FPGA vendor's documentation.
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//
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module basic_rom(
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input wire clk,
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input wire [13:0] address_in,
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output wire [7:0] data_out,
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input wire [7:0] data_in,
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input wire wr,
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input wire cs
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);
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(* ROM_STYLE="BLOCK" *)
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reg [7:0] basic [0:16383];
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reg [7:0] data;
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reg cs_prev=1'b1;
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wire enable;
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always@(posedge clk) begin
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if (wr)
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basic[address_in] <= data_in;
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if(enable)
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data<=basic[address_in];
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end
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always@(posedge clk)
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cs_prev<=cs;
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assign enable=~cs&cs_prev; // cs falling edge detection
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assign data_out=(~cs)?data:8'hff;
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initial begin
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$readmemh("roms/basic.hex",basic);
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end
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endmodule
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