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96 lines
2.2 KiB
Verilog
96 lines
2.2 KiB
Verilog
// Ein einfaches System-on-a-chip (SOC)
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// (c) 2015 Till Harbaum
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module soc (
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input [1:0] CLOCK_27,
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output SDRAM_nCS,
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output VGA_HS,
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output VGA_VS,
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B
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);
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// Deaktivieren des unbenutzten SDRAMs
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assign SDRAM_nCS = 1;
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wire pixel_clock;
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// Einbinden des VGA-Controllers
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vga vga (
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.pclk ( pixel_clock ),
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.cpu_clk ( cpu_clock ),
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.cpu_wr ( !cpu_wr_n && !cpu_addr[15] ),
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.cpu_addr ( cpu_addr[13:0] ),
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.cpu_data ( cpu_dout ),
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.hs (VGA_HS),
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.vs (VGA_VS),
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.r (VGA_R),
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.g (VGA_G),
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.b (VGA_B)
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);
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// CPU bekommt die ersten 256 CPU-Taktzyklen einen Reset
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reg [7:0] cpu_reset_cnt = 8'h00;
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wire cpu_reset = (cpu_reset_cnt != 255);
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always @(posedge cpu_clock)
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if(cpu_reset_cnt != 255)
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cpu_reset_cnt <= cpu_reset_cnt + 8'd1;
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// CPU-Steuersignale
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wire cpu_clock;
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wire [15:0] cpu_addr;
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wire [7:0] cpu_din;
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wire [7:0] cpu_dout;
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wire cpu_rd_n;
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wire cpu_wr_n;
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wire cpu_mreq_n;
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// Einbinden der Z80-CPU
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T80s T80s (
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.RESET_n ( !cpu_reset ),
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.CLK_n ( cpu_clock ),
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.WAIT_n ( 1'b1 ),
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.INT_n ( 1'b1 ),
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.NMI_n ( 1'b1 ),
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.BUSRQ_n ( 1'b1 ),
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.MREQ_n ( cpu_mreq_n ),
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.RD_n ( cpu_rd_n ),
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.WR_n ( cpu_wr_n ),
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.A ( cpu_addr ),
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.DI ( cpu_din ),
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.DO ( cpu_dout )
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);
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// RAM wird in oberer Haelfte des Adressraums gelesen (A15=1),
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// ROM in unserer (A15=0)
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wire [7:0] ram_data_out, rom_data_out;
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assign cpu_din = cpu_addr[15]?ram_data_out:rom_data_out;
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// Einbinden des 4k Programmcodes im boot_rom
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boot_rom boot_rom (
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.clock ( cpu_clock ),
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.address ( cpu_addr[11:0] ),
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.q ( rom_data_out )
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);
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// Einbinden des 4k RAM
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ram4k ram4k (
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.clock ( cpu_clock ),
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.address ( cpu_addr[11:0] ),
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.wren ( !cpu_wr_n && cpu_addr[15] ),
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.data ( cpu_dout ),
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.q ( ram_data_out )
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);
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// PLL, um aus den 27MHz den VGA-Pixeltakt und den CPU-Takt zu erzeugen
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pll pll (
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.inclk0 ( CLOCK_27[0] ),
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.c0 ( pixel_clock ), // 25.175 MHz
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.c1 ( cpu_clock ) // 4 MHz
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);
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endmodule
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