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125 lines
3.6 KiB
Verilog
125 lines
3.6 KiB
Verilog
// A simple system-on-a-chip (SoC) for the MiST
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// (c) 2016 Till Harbaum
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// video controller generating 160x100 pixles. The video mode is based
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// upon a non-interlaced PAL or NTSC TV mode.
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module video (
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// pixel clock
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input pclk,
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// config input
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input pal,
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// CPU interface (write only!)
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input cpu_clk,
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input cpu_wr,
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input [13:0] cpu_addr,
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input [7:0] cpu_data,
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// output to VGA screen
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output reg hs,
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output reg vs,
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output [5:0] r,
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output [5:0] g,
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output [5:0] b
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);
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// PAL timing:
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// 864 pixel total horizontal @ 13.5 Mhz = 15.625 kHz
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// 312 lines vertically @ 15.625 kHz = 50.08 Hz
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// NTSC timing:
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// 858 pixel total horizontal @ 13.5 Mhz = 15.735 kHz
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// 262 lines vertically @ 15.735 kHz = 60.05 Hz
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parameter H = 640; // width of visible area
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wire [9:0] hfp = pal?51:56; // unused time before hsync
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wire [9:0] hsw = pal?63:63; // width of hsync
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wire [9:0] hbp = pal?110:99; // unused time after hsync
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parameter V = 200; // height of visible area
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wire [9:0] vfp = pal?46:23; // unused time before vsync
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wire [9:0] vsw = pal?2:3; // width of vsync
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wire [9:0] vbp = pal?64:36; // unused time after vsync
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reg[9:0] h_cnt; // horizontal pixel counter
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reg[9:0] v_cnt; // vertical pixel counter
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// horizontal pixel counter
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always@(posedge pclk) begin
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if(h_cnt==H+hfp+hsw+hbp-1) h_cnt <= 10'd0;
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else h_cnt <= h_cnt + 10'd1;
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// generate negative hsync signal
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if(h_cnt == H+hfp) hs <= 1'b0;
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if(h_cnt == H+hfp+hsw) hs <= 1'b1;
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end
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// veritical pixel counter
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always@(posedge pclk) begin
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// the vertical counter is processed at the begin of each hsync
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if(h_cnt == H+hfp) begin
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if(v_cnt==vsw+vbp+V+vfp-1) v_cnt <= 10'd0;
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else v_cnt <= v_cnt + 10'd1;
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// generate negative vsync signal
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if(v_cnt == V+vfp) vs <= 1'b0;
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if(v_cnt == V+vfp+vsw) vs <= 1'b1;
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end
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end
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// 16000 bytes of internal video memory for 160x100 pixel at 8 Bit (RGB 332)
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reg [7:0] vmem [160*100-1:0];
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reg [13:0] video_counter;
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reg [7:0] pixel;
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// write VRAM via CPU interface
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always @(posedge cpu_clk)
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if(cpu_wr)
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vmem[cpu_addr] <= cpu_data;
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// read VRAM for video generation
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always@(posedge pclk) begin
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// The video counter is being reset at the begin of each vsync.
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// Otherwise it's increased every fourth pixel in the visible area.
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// At the end of the first three of four lines the counter is
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// decreased by the total line length to display the same contents
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// for four lines so 100 different lines are displayed on the 400
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// VGA lines.
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// visible area?
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if((v_cnt < V) && (h_cnt < H)) begin
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// increase video counter after each pixel
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if(h_cnt[1:0] == 2'd3)
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video_counter <= video_counter + 14'd1;
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pixel <= vmem[video_counter]; // read VRAM
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end else begin
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// video counter is manipulated at the end of a line outside
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// the visible area
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if(h_cnt == H+hfp) begin
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// the video counter is reset at the begin of the vsync
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// at the end of every second line it's decremented
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// one line to repeat the same pixels over two display
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// lines
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if(v_cnt == V+vfp)
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video_counter <= 14'd0;
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else if((v_cnt < V) && (v_cnt[0] != 2'd1))
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video_counter <= video_counter - 14'd160;
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end
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pixel <= 8'h00; // color outside visible area: black
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end
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end
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// split the 8 rgb bits into the three base colors. Every second line is
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// darker to give some scanlines effect
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assign r = { pixel[7:5], 3'b000 };
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assign g = { pixel[4:2], 3'b000 };
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assign b = { pixel[1:0], 4'b0000 };
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endmodule
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