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125 lines
2.3 KiB
Verilog
125 lines
2.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 09:29:12 07/19/2012
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// Design Name:
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// Module Name: spi
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module spi (
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input CLOCK,
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input nRESET,
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input CLKEN,
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input ENABLE,
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input nWR,
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input [7:0] DI,
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output[7:0] DO,
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input DUMMY,
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output reg DONE,
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output SD_CS,
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output SD_CLK,
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output SD_MOSI,
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input SD_MISO
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);
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reg [4:0] counter;
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assign SD_MOSI = shift_reg[8];
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// Shift register has an extra bit because we write on the
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// falling edge and read on the rising edge
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reg [8:0] shift_reg;
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reg [7:0] in_reg;
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reg quad_mode;
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reg dummy;
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assign DO = in_reg;
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// SD card outputs from clock divider and shift register
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assign SD_CLK = counter[0];
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// SPI write
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always @(posedge CLOCK) begin
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if (nRESET === 1'b 0) begin
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shift_reg <= {9{1'b 1}};
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in_reg <= {8{1'b 1}};
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counter <= 5'b 01111; // Idle
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DONE <= 1'b0;
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dummy <= 1'b0;
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end else if (CLKEN === 1'b 1) begin
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DONE <= 1'b0;
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if (((counter === 5'b 01111) & !dummy) | ((counter === 5'b10001) & dummy)) begin
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// Store previous shift register value in input register
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in_reg <= shift_reg[7:0];
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DONE <= 1'b1;
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// Idle - check for a bus access
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if (ENABLE === 1'b 1) begin
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// Write loads shift register with data
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// Read loads it with all 1s
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if (nWR === 1'b 1) begin
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shift_reg <= {9{1'b 1}};
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end else begin
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shift_reg <= {DI, 1'b 1};
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end
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dummy <= DUMMY;
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counter <= 5'b 00000; // Initiates transfer
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end
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// Transfer in progress
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end else begin
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counter <= counter + 4'd1;
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if (counter[0] === 1'b 0) begin
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shift_reg[0] <= SD_MISO;
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// Output next bit on falling edge
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end else begin
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shift_reg <= {shift_reg[7:0], 1'b 1};
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end
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end
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end
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end
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assign SD_CS = !nRESET;
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endmodule // module flash
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