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129 lines
4.5 KiB
Verilog
129 lines
4.5 KiB
Verilog
`timescale 1ns / 1ps
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/*Copyright (c) 2012, Stephen J Leary
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the author nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL STEPHEN J LEARY BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module address_decode(
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input [15:0] cpu_a,
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input [3:0] romsel,
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output ddr_enable,
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// Memory enables
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output ram_enable,
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// 0x0000
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output rom_enable,
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// 0x8000 (BASIC/sideways ROMs)
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output mos_enable,
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// 0xC000
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// IO region enables
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output io_fred,
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// 0xFC00 (1 MHz bus)
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output io_jim,
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// 0xFD00 (1 MHz bus)
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output io_sheila,
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// 0xFE00 (System peripherals)
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// SHIELA
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output crtc_enable,
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// 0xFE00-FE07
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output acia_enable,
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// 0xFE08-FE0F
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output serproc_enable,
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// 0xFE10-FE1F
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output vidproc_enable,
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// 0xFE20-FE2F
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output romsel_enable,
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// 0xFE30-FE3F
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output sys_via_enable,
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// 0xFE40-FE5F
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output user_via_enable,
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// 0xFE60-FE7F
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output fddc_enable,
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// 0xFE80-FE9F
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output adlc_enable,
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// 0xFEA0-FEBF (Econet)
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output adc_enable,
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// 0xFEC0-FEDF
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output tube_enable,
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// 0xFEE0-FEFF
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output mhz1_enable
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);
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// Set for access to any 1 MHz peripheral
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// Address decoding
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// 0x0000 = 32 KB SRAM
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// 0x8000 = 16 KB BASIC/Sideways ROMs
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// 0xC000 = 16 KB MOS ROM
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//
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// IO regions are mapped into a hole in the MOS. There are three regions:
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// 0xFC00 = FRED
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// 0xFD00 = JIM
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// 0xFE00 = SHEILA
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assign ddr_enable = (!romsel[3] & (cpu_a[15:14] === 2'b10));
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assign ram_enable = ~cpu_a[15];
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assign rom_enable = cpu_a[15] & ~cpu_a[14];
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assign mos_enable = cpu_a[15] & cpu_a[14] & ~(io_fred | io_jim | io_sheila);
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assign io_fred = cpu_a[15:8] === 8'b 11111100 ? 1'b 1 : 1'b 0;
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assign io_jim = cpu_a[15:8] === 8'b 11111101 ? 1'b 1 : 1'b 0;
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assign io_sheila = cpu_a[15:8] === 8'b 11111110 ? 1'b 1 : 1'b 0;
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// The following IO regions are accessed at 1 MHz and hence will stall the
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// CPU accordingly
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assign mhz1_enable = io_fred | io_jim | adc_enable | sys_via_enable |
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user_via_enable | serproc_enable | acia_enable | crtc_enable;
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// SHEILA address demux
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// All the system peripherals are mapped into this page as follows:
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// 0xFE00 - 0xFE07 = MC6845 CRTC
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// 0xFE08 - 0xFE0F = MC6850 ACIA (Serial/Tape)
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// 0xFE10 - 0xFE1F = Serial ULA
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// 0xFE20 - 0xFE2F = Video ULA
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// 0xFE30 - 0xFE3F = Paged ROM select latch
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// 0xFE40 - 0xFE5F = System VIA (6522)
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// 0xFE60 - 0xFE7F = User VIA (6522)
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// 0xFE80 - 0xFE9F = 8271 Floppy disc controller
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// 0xFEA0 - 0xFEBF = 68B54 ADLC for Econet
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// 0xFEC0 - 0xFEDF = uPD7002 ADC
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// 0xFEE0 - 0xFEFF = Tube ULA
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assign crtc_enable = io_sheila & (cpu_a[7:3] === 'd0);
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assign acia_enable = io_sheila & (cpu_a[7:3] === 'd1);
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assign serproc_enable = io_sheila & (cpu_a[7:4] === 'b0001);
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assign vidproc_enable = io_sheila & (cpu_a[7:4] === 'b0010);
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assign romsel_enable = io_sheila & (cpu_a[7:4] === 'b0011);
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assign sys_via_enable = io_sheila & (cpu_a[7:5] === 'b010);
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assign user_via_enable = io_sheila & (cpu_a[7:5] === 'b011);
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assign fddc_enable = io_sheila & (cpu_a[7:5] === 'b100);
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assign adlc_enable = io_sheila & (cpu_a[7:5] === 'b101);
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assign adc_enable = io_sheila & (cpu_a[7:5] === 'b110);
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assign tube_enable = io_sheila & (cpu_a[7:5] === 'b111);
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endmodule
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