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121 lines
3.9 KiB
Verilog
Executable File
121 lines
3.9 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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/*
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Copyright (c) 2012, Stephen J Leary
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the author nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL STEPHEN J LEARY BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module clocks(
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input clk_32m,
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input clk_24m,
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input reset_n,
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input mhz1_enable,
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output wire mhz4_clken,
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output wire mhz2_clken,
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output wire mhz1_clken,
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output wire cpu_cycle,
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output wire cpu_clken,
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output wire vid_clken,
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output wire ttxt_clken,
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output wire ttxt_clkenx2,
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output wire tube_clken
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);
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reg [4:0] clken_counter;
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reg [1:0] cpu_cycle_mask;
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// SAA5050 needs a 6 MHz clock enable relative to a 24 MHz clock
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reg [1:0] ttxt_clken_counter;
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// Clock enable generation - 32 MHz clock split into 32 cycles^M
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// CPU is on 0 and 16 (but can be masked by 1 MHz bus accesses)^M
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// Video is on all odd cycles (16 MHz)^M
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// 1 MHz cycles are on cycle 31 (1 MHz) ^M
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assign vid_clken = clken_counter[0]; // & ~vsync_latch & ~hsync_latch;
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// 1,3,5...^M
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assign mhz4_clken = clken_counter[0] & clken_counter[1] & clken_counter[2];
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// 7/15/23/31^M
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assign mhz2_clken = mhz4_clken & clken_counter[3];
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// 1/17
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assign tube_clken = clken_counter[0] & !clken_counter[1] & !clken_counter[2];
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// 15/31^M
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assign mhz1_clken = mhz2_clken & clken_counter[4];
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// 31^M
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assign cpu_cycle = ~(clken_counter[0] | clken_counter[1] | clken_counter[2] | clken_counter[3]);
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// 0/16^M
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assign cpu_clken = cpu_cycle & ~cpu_cycle_mask[1] & ~cpu_cycle_mask[0];
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always @(posedge clk_32m)
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begin : clk_gen
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// if (reset_n === 1'b 0)
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// begin
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// clken_counter <= {5{1'b 0}};
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// end
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// else
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// begin
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clken_counter <= clken_counter + 5'd1;
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// end
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end
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always @(posedge clk_32m)
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begin : cycle_stretch
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if (reset_n === 1'b 0) begin
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cpu_cycle_mask <= 2'b 00;
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end
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else if (mhz2_clken === 1'b 1 ) begin
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if ((mhz1_enable === 1'b 1) && (cpu_cycle_mask === 2'b 00)) begin
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// Block CPU cycles until 1 MHz cycle has completed
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if (mhz1_clken === 1'b 0) begin
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cpu_cycle_mask <= 2'b 01;
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end else begin
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cpu_cycle_mask <= 2'b 10;
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end
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end
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if (cpu_cycle_mask !== 2'b 00) begin
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cpu_cycle_mask <= cpu_cycle_mask - 2'b 01;
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end
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end
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end
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always @(posedge clk_24m)
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begin : ttxt_clk_gen
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if (reset_n === 1'b 0) begin
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ttxt_clken_counter <= {2{1'b 0}};
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end else begin
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ttxt_clken_counter <= ttxt_clken_counter + 1'd1;
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end
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end
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// 6 MHz clock enable for SAA5050
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assign ttxt_clken = ttxt_clken_counter === 0 ? 1'b 1 : 1'b 0;
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assign ttxt_clkenx2 = !ttxt_clken_counter[0];
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endmodule
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