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77 lines
2.3 KiB
Verilog
77 lines
2.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Copyright 2013-2016 Istvan Hegedus
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//
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// FPGATED is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// FPGATED is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// Create Date: 11:30:06 12/14/2015
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// Module Name: ps2receiver.v
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// Project Name: FPGATED
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// Description: PS2 keyboard receiver
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//
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//
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//
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// Revision:
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// Revision 1.0 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ps2receiver(
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input clk,
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input ps2_clk,
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input ps2_data,
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output reg rx_done,
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output reg [7:0] ps2scancode
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);
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reg ps2clkreg=1'b0,prev_ps2clkreg=1'b0;
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reg [3:0] receivedbits=4'b0;
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reg [11:0] watchdog=12'd2900; // ~ 100us watchdog period with 28MHz clock
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reg [7:0] ps2clkfilter;
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reg [10:0] shiftreg;
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always @(posedge clk) // filtering ps2 clock line glitches
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begin
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ps2clkfilter<={ps2clkfilter[6:0],ps2_clk};
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if(ps2clkfilter==8'h00)
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ps2clkreg<=0;
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else if (ps2clkfilter==8'hff)
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ps2clkreg<=1;
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prev_ps2clkreg<=ps2clkreg; // this is needed for clock edge detection
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end
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always @(posedge clk)
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begin
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rx_done<=0; // rx_done is active only for one clk cycle
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if(watchdog==0) // when watchdog timer expires, reset received bits
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receivedbits<=0;
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else watchdog<=watchdog-1'd1;
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if(prev_ps2clkreg & ~ps2clkreg) // falling edge of ps2 clock
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begin
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watchdog<=12'd2900; // reload watchdog timer
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shiftreg<={ps2_data,shiftreg[10:1]};
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receivedbits<=receivedbits+1'd1;
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end
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if(receivedbits==4'd11)
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begin
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ps2scancode<=shiftreg[8:1];
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rx_done<=1;
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receivedbits<=0;
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end
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end
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endmodule
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