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254 lines
7.7 KiB
Verilog
254 lines
7.7 KiB
Verilog
module sid8580 (clk_1MHz, clk32, reset, cs, we, addr, data_in, data_out,
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pot_x, pot_y, audio_data, extfilter_en);
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// Input Ports
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input wire [0:0] clk_1MHz;
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input wire [0:0] clk32;
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input wire [0:0] reset;
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input wire [0:0] cs;
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input wire [0:0] we;
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input wire [4:0] addr;
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input wire [7:0] data_in;
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input wire [7:0] pot_x;
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input wire [7:0] pot_y;
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input wire [0:0] extfilter_en;
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// Output Ports
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output wire [ 7:0] data_out;
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output wire [15:0] audio_data;
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// Internal Signals
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reg [7:0] Voice_1_Freq_lo;
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reg [7:0] Voice_1_Freq_hi;
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reg [7:0] Voice_1_Pw_lo;
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reg [3:0] Voice_1_Pw_hi;
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reg [7:0] Voice_1_Control;
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reg [7:0] Voice_1_Att_dec;
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reg [7:0] Voice_1_Sus_Rel;
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reg [7:0] Voice_2_Freq_lo;
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reg [7:0] Voice_2_Freq_hi;
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reg [7:0] Voice_2_Pw_lo;
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reg [3:0] Voice_2_Pw_hi;
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reg [7:0] Voice_2_Control;
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reg [7:0] Voice_2_Att_dec;
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reg [7:0] Voice_2_Sus_Rel;
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reg [7:0] Voice_3_Freq_lo;
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reg [7:0] Voice_3_Freq_hi;
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reg [7:0] Voice_3_Pw_lo;
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reg [3:0] Voice_3_Pw_hi;
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reg [7:0] Voice_3_Control;
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reg [7:0] Voice_3_Att_dec;
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reg [7:0] Voice_3_Sus_Rel;
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reg [7:0] Filter_Fc_lo;
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reg [7:0] Filter_Fc_hi;
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reg [7:0] Filter_Res_Filt;
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reg [7:0] Filter_Mode_Vol;
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wire [7:0] Misc_Osc3_Random;
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wire [7:0] Misc_Env3;
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reg [7:0] Ext_hi;
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reg [3:0] Ext_lo;
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reg [7:0] do_buf;
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reg [7:0] sidrandom;
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wire [11:0] voice_1;
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wire [11:0] voice_2;
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wire [11:0] voice_3;
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wire [17:0] voice_mixed;
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reg [17:0] voice_volume;
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wire [ 0:0] voice_1_PA_MSB;
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wire [ 0:0] voice_2_PA_MSB;
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wire [ 0:0] voice_3_PA_MSB;
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wire [18:0] filtered_audio;
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reg [ 0:0] tick_q1;
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reg [ 0:0] tick_q2;
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reg [ 0:0] input_valid;
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wire [17:0] unsigned_audio;
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wire [18:0] unsigned_filt;
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reg [ 0:0] ff1;
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localparam DC_offset = 14'b00111111111111;
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// Voice 1 Instantiation
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sid_voice v1 (.clock(clk_1MHz), .reset(reset),
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.freq_lo(Voice_1_Freq_lo), .freq_hi(Voice_1_Freq_hi),
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.pw_lo(Voice_1_Pw_lo), .pw_hi(Voice_1_Pw_hi),
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.control(Voice_1_Control),
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.att_dec(Voice_1_Att_dec), .sus_rel(Voice_1_Sus_Rel),
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.osc_msb_in(voice_3_PA_MSB), .osc_msb_out(voice_1_PA_MSB),
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.signal_out(voice_1));
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// Voice 2 Instantiation
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sid_voice v2 (.clock(clk_1MHz), .reset(reset),
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.freq_lo(Voice_2_Freq_lo), .freq_hi(Voice_2_Freq_hi),
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.pw_lo(Voice_2_Pw_lo), .pw_hi(Voice_2_Pw_hi),
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.control(Voice_2_Control),
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.att_dec(Voice_2_Att_dec), .sus_rel(Voice_2_Sus_Rel),
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.osc_msb_in(voice_1_PA_MSB), .osc_msb_out(voice_2_PA_MSB),
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.signal_out(voice_2));
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// Voice 3 Instantiation
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sid_voice v3 (.clock(clk_1MHz), .reset(reset),
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.freq_lo(Voice_3_Freq_lo), .freq_hi(Voice_3_Freq_hi),
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.pw_lo(Voice_3_Pw_lo), .pw_hi(Voice_3_Pw_hi),
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.control(Voice_3_Control),
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.att_dec(Voice_3_Att_dec), .sus_rel(Voice_3_Sus_Rel),
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.osc_msb_in(voice_2_PA_MSB), .osc_msb_out(voice_3_PA_MSB),
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.signal_out(voice_3), .osc_out(Misc_Osc3_Random),
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.env_out(Misc_Env3));
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// Filter Instantiation
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sid_filters filters (.clk(clk32), .rst(reset),
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.Fc_lo(Filter_Fc_lo), .Fc_hi(Filter_Fc_hi),
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.Res_Filt(Filter_Res_Filt), .Mode_Vol(Filter_Mode_Vol),
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.voice1(voice_1), .voice2(voice_2),
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.voice3(voice_3), .input_valid(input_valid),
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.ext_in(12'hfff), .sound(audio_data),
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.extfilter_en(extfilter_en));
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assign data_out = do_buf;
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//assign audio_data = {1'b0, (filtered_audio[18:5] + 14'b1000000000000000)};
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//assign unsigned_filt = filtered_audio + 19'b1000000000000000000;
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//assign unsigned_audio = unsigned_filt[18:1];
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//assign audio_data = filtered_audio[18:3];// + 15'h4000;//{1'b0, unsigned_audio[17:1]};
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// Toggle Flip Flop
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always @(posedge clk_1MHz)
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begin
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if (reset)
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ff1 <= 1'b0;
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else
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ff1 <= ~ff1;
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end
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always @(posedge clk32)
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begin
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input_valid <= (tick_q1 != tick_q2) ? 1'b1 : 1'b0;
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tick_q1 <= ff1;
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tick_q2 <= tick_q1;
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end
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reg [7:0] last_wr;
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// Register Decoding
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always @(posedge clk32)
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begin
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if (reset)
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begin
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Voice_1_Freq_lo <= 8'h00;
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Voice_1_Freq_hi <= 8'h00;
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Voice_1_Pw_lo <= 8'h00;
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Voice_1_Pw_hi <= 4'h0;
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Voice_1_Control <= 8'h00;
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Voice_1_Att_dec <= 8'h00;
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Voice_1_Sus_Rel <= 8'h00;
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Voice_2_Freq_lo <= 8'h00;
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Voice_2_Freq_hi <= 8'h00;
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Voice_2_Pw_lo <= 8'h00;
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Voice_2_Pw_hi <= 4'h0;
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Voice_2_Control <= 8'h00;
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Voice_2_Att_dec <= 8'h00;
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Voice_2_Sus_Rel <= 8'h00;
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Voice_3_Freq_lo <= 8'h00;
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Voice_3_Freq_hi <= 8'h00;
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Voice_3_Pw_lo <= 8'h00;
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Voice_3_Pw_hi <= 4'h0;
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Voice_3_Control <= 8'h00;
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Voice_3_Att_dec <= 8'h00;
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Voice_3_Sus_Rel <= 8'h00;
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Filter_Fc_lo <= 8'h00;
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Filter_Fc_hi <= 8'h00;
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Filter_Res_Filt <= 8'h00;
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Filter_Mode_Vol <= 8'h00;
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Ext_hi <= 8'h00;
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Ext_lo <= 4'h0;
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end
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else
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begin
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Voice_1_Freq_lo <= Voice_1_Freq_lo;
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Voice_1_Freq_hi <= Voice_1_Freq_hi;
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Voice_1_Pw_lo <= Voice_1_Pw_lo;
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Voice_1_Pw_hi <= Voice_1_Pw_hi;
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Voice_1_Control <= Voice_1_Control;
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Voice_1_Att_dec <= Voice_1_Att_dec;
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Voice_1_Sus_Rel <= Voice_1_Sus_Rel;
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Voice_2_Freq_lo <= Voice_2_Freq_lo;
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Voice_2_Freq_hi <= Voice_2_Freq_hi;
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Voice_2_Pw_lo <= Voice_2_Pw_lo;
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Voice_2_Pw_hi <= Voice_2_Pw_hi;
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Voice_2_Control <= Voice_2_Control;
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Voice_2_Att_dec <= Voice_2_Att_dec;
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Voice_2_Sus_Rel <= Voice_2_Sus_Rel;
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Voice_3_Freq_lo <= Voice_3_Freq_lo;
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Voice_3_Freq_hi <= Voice_3_Freq_hi;
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Voice_3_Pw_lo <= Voice_3_Pw_lo;
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Voice_3_Pw_hi <= Voice_3_Pw_hi;
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Voice_3_Control <= Voice_3_Control;
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Voice_3_Att_dec <= Voice_3_Att_dec;
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Voice_3_Sus_Rel <= Voice_3_Sus_Rel;
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Filter_Fc_lo <= Filter_Fc_lo;
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Filter_Fc_hi <= Filter_Fc_hi;
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Filter_Res_Filt <= Filter_Res_Filt;
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Filter_Mode_Vol <= Filter_Mode_Vol;
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Ext_hi <= Ext_hi;
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Ext_lo <= Ext_lo;
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do_buf <= 8'h00;
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end
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if (cs)
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begin
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if (we)
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begin
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last_wr <= data_in;
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case (addr)
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5'h00: Voice_1_Freq_lo <= data_in;
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5'h01: Voice_1_Freq_hi <= data_in;
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5'h02: Voice_1_Pw_lo <= data_in;
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5'h03: Voice_1_Pw_hi <= data_in[3:0];
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5'h04: Voice_1_Control <= data_in;
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5'h05: Voice_1_Att_dec <= data_in;
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5'h06: Voice_1_Sus_Rel <= data_in;
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5'h07: Voice_2_Freq_lo <= data_in;
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5'h08: Voice_2_Freq_hi <= data_in;
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5'h09: Voice_2_Pw_lo <= data_in;
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5'h0a: Voice_2_Pw_hi <= data_in[3:0];
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5'h0b: Voice_2_Control <= data_in;
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5'h0c: Voice_2_Att_dec <= data_in;
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5'h0d: Voice_2_Sus_Rel <= data_in;
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5'h0e: Voice_3_Freq_lo <= data_in;
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5'h0f: Voice_3_Freq_hi <= data_in;
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5'h10: Voice_3_Pw_lo <= data_in;
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5'h11: Voice_3_Pw_hi <= data_in[3:0];
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5'h12: Voice_3_Control <= data_in;
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5'h13: Voice_3_Att_dec <= data_in;
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5'h14: Voice_3_Sus_Rel <= data_in;
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5'h15: Filter_Fc_lo <= data_in;
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5'h16: Filter_Fc_hi <= data_in;
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5'h17: Filter_Res_Filt <= data_in;
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5'h18: Filter_Mode_Vol <= data_in;
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5'h19: Ext_lo <= data_in[3:0];
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5'h1a: Ext_hi <= data_in;
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default:;
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endcase
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end
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else
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begin
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case (addr)
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5'h19: do_buf <= pot_x;
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5'h1a: do_buf <= pot_y;
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5'h1b: do_buf <= Misc_Osc3_Random;
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5'h1c: do_buf <= Misc_Env3;
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default: do_buf <= last_wr;
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endcase
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end
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end
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end
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endmodule
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