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96 lines
2.4 KiB
VHDL
96 lines
2.4 KiB
VHDL
---------------------------------------------------------------------------------
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-- composite_sync by Dar (darfpga@aol.fr)
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-- http://darfpga.blogspot.fr
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--
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-- Generate composite sync and blank for tv mode from h/v syncs
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--
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---------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.numeric_std.all;
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entity composite_sync is
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port(
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clk32 : in std_logic;
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hsync : in std_logic;
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vsync : in std_logic;
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ntsc : in std_logic;
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hsync_out : out std_logic;
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vsync_out : out std_logic;
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blank : out std_logic
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);
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end composite_sync ;
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architecture struct of composite_sync is
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signal clk_cnt : std_logic_vector(1 downto 0);
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signal vsync_r : std_logic;
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signal hsync_r : std_logic;
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signal hsync_r0 : std_logic;
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signal vblank : std_logic;
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signal hblank : std_logic;
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begin
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blank <= hblank or vblank;
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process(clk32)
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variable dot_count : integer range 0 to 1023 := 0;
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variable line_count : integer range 0 to 511 := 0;
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begin
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if falling_edge(clk32) then
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hsync_r0 <= hsync;
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if hsync_r0 = '0' and hsync = '1' then
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clk_cnt <= "00";
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else
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clk_cnt <= clk_cnt + '1';
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end if;
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end if;
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if rising_edge(clk32) then
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if clk_cnt = "00" then
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vsync_r <= vsync;
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hsync_r <= hsync;
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if hsync_r = '0' and hsync = '1' then
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dot_count := 0;
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line_count := line_count + 1;
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else
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dot_count := dot_count + 1;
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end if;
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if vsync_r = '0' and vsync = '1' then
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line_count := 0;
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end if;
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if ntsc = '1' then
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if dot_count = 510 then hblank <= '1'; end if;
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if dot_count = 010 then hsync_out <= '1'; end if;
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if dot_count = 048 then hsync_out <= '0'; end if;
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if dot_count = 096 then hblank <= '0'; end if;
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if line_count = 260 then vblank <= '1'; end if;
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if line_count = 262 then vsync_out <= '1'; end if;
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if line_count = 008 then vsync_out <= '0'; end if;
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if line_count = 010 then vblank <= '0'; end if;
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else
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if dot_count = 495 then hblank <= '1'; end if;
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if dot_count = 010 then hsync_out <= '1'; end if;
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if dot_count = 048 then hsync_out <= '0'; end if;
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if dot_count = 094 then hblank <= '0'; end if;
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if line_count = 306 then vblank <= '1'; end if;
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if line_count = 308 then vsync_out <= '1'; end if;
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if line_count = 004 then vsync_out <= '0'; end if;
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if line_count = 006 then vblank <= '0'; end if;
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end if;
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end if;
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end if;
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end process;
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end architecture; |