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146 lines
3.9 KiB
Verilog
146 lines
3.9 KiB
Verilog
// acsi.v
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//
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// Atari ST ACSI implementation for the MIST baord
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module acsi (
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// clocks and system interface
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input clk,
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input reset,
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input [7:0] enable,
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input dma_ack, // IO controller answers request
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input dma_nak, // IO controller rejects request
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input [7:0] dma_status,
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input [3:0] status_sel, // 10 command bytes + 1 status byte
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output [7:0] status_byte,
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// cpu interface
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input [1:0] cpu_addr,
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input cpu_sel,
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input cpu_rw,
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input [7:0] cpu_din,
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output [7:0] cpu_dout,
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output reg irq
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);
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// acsi always returns dma status on cpu_read
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assign cpu_dout = dma_status;
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// Total number of command bytes:
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// cmd 0..1f -> 6
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// cmd 20..5f -> 10
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// cmd 80..9f -> 16
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// cmd a0..bf -> 12
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wire [7:0] cmd_code = cmd_parameter[0];
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wire [3:0] parms =
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((cmd_code >= 8'h00)&&(cmd_code <= 8'h1f))?5:
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((cmd_code >= 8'h20)&&(cmd_code <= 8'h5f))?9:
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((cmd_code >= 8'h80)&&(cmd_code <= 8'h9f))?15:
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11;
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reg [2:0] target;
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reg [3:0] byte_counter;
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reg [7:0] cmd_parameter [15:0];
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reg busy;
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// acsi status as reported to the io controller
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assign status_byte =
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(status_sel == 0)?cmd_parameter[0]:
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(status_sel == 1)?cmd_parameter[1]:
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(status_sel == 2)?cmd_parameter[2]:
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(status_sel == 3)?cmd_parameter[3]:
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(status_sel == 4)?cmd_parameter[4]:
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(status_sel == 5)?cmd_parameter[5]:
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(status_sel == 6)?cmd_parameter[6]:
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(status_sel == 7)?cmd_parameter[7]:
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(status_sel == 8)?cmd_parameter[8]:
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(status_sel == 9)?cmd_parameter[9]:
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(status_sel == 10)?{ target, 4'b0000000, busy }:
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8'h00;
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// CPU write interface
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always @(negedge clk) begin
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if(reset) begin
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target <= 3'd0;
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irq <= 1'b0;
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busy <= 1'b0;
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end else begin
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// DMA transfer has been ack'd by io controller
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if(dma_ack && busy) begin
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irq <= 1'b1; // set acsi irq
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busy <= 1'd0;
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end
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// DMA transfer has been rejected by io controller (no such device)
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if(dma_nak)
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busy <= 1'd0;
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// cpu is accessing acsi bus -> clear acsi irq
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// status itself is returned by the io controller with the dma_ack.
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if(cpu_sel)
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irq <= 1'b0;
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// acsi register access
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if(cpu_sel && !cpu_rw) begin
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if(!cpu_addr[0]) begin
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// a0 == 0 -> first command byte
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target <= cpu_din[7:5];
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// icd command?
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if(cpu_din[4:0] == 5'h1f)
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byte_counter <= 3'd0; // next byte will contain first command byte
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else begin
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cmd_parameter[0] <= { 3'd0, cpu_din[4:0] };
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byte_counter <= 3'd1; // next byte will contain second command byte
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end
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// check if this acsi device is enabled
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if(enable[cpu_din[7:5]] == 1'b1)
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irq <= 1'b1;
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end else begin
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// if(byte_counter < 15) begin
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// further bytes
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cmd_parameter[byte_counter] <= cpu_din;
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byte_counter <= byte_counter + 3'd1;
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// check if this acsi device is enabled
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if(enable[target] == 1'b1) begin
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// auto-ack first 5 bytes, 6 bytes in case of icd command
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if(byte_counter < parms)
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irq <= 1'b1;
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else
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busy <= 1'b1; // request io cntroller
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end
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end
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// end
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end
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end
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end
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endmodule // acsi
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