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16 lines
211 B
Verilog
16 lines
211 B
Verilog
module font (
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input clk,
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input [9:0] a,
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output reg [7:0] d
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);
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always @(posedge clk)
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d <= rom[a];
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reg [7:0] rom [0:767];
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initial $readmemh("font8x8.memh",rom);
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endmodule // font
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