mirror of
https://github.com/mist-devel/mist-board.git
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434 lines
13 KiB
Verilog
434 lines
13 KiB
Verilog
// mfp.v
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//
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// Atari ST multi function peripheral (MFP) for the MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module mfp (
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// cpu register interface
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input clk,
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input reset,
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input [7:0] din,
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input sel,
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input [4:0] addr,
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input ds,
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input rw,
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output reg [7:0] dout,
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output irq,
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input iack,
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// serial rs232 connection to io controller
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output serial_data_out_available,
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input serial_strobe_out,
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output [7:0] serial_data_out,
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output [63:0] serial_status_out,
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// serial rs223 connection from io controller
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input serial_strobe_in,
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input [7:0] serial_data_in,
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output serial_data_in_full,
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input [7:0] serial_status_in,
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// inputs
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input clk_ext, // external 2.457MHz
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input [1:0] t_i, // timer input
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input [7:0] i // input port
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);
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wire serial_data_out_fifo_full;
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// --- mfp output fifo ---
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// filled by the CPU when writing to the mfp uart data register
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// emptied by the io controller when reading via SPI
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io_fifo mfp_out_fifo (
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.reset (reset),
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.in_clk (!clk), // latch incoming data on negedge
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.in (din),
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.in_strobe (1'b0),
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.in_enable (sel && ~ds && ~rw && (addr == 5'h17)),
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.out_clk (clk),
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.out (serial_data_out),
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.out_strobe (serial_strobe_out),
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.out_enable (1'b0),
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.full (serial_data_out_fifo_full),
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.data_available (serial_data_out_available)
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);
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// --- mfp input fifo ---
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// filled by the io controller when writing via SPI
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// emptied by CPU when reading the mfp uart data register
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io_fifo mfp_in_fifo (
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.reset (reset),
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.in_clk (!clk), // latch incoming data on negedge
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.in (serial_data_in),
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.in_strobe (serial_strobe_in),
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.in_enable (1'b0),
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.out_clk (!clk),
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.out (serial_data_in_cpu),
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.out_strobe (1'b0),
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.out_enable (serial_cpu_data_read && serial_data_in_available),
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.space (serial_data_in_space),
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.empty (serial_data_in_empty),
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.full (serial_data_in_full),
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.data_available (serial_data_in_available)
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);
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// ---------------- mfp uart data to/from io controller ------------
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reg serial_cpu_data_read, serial_cpu_data_readD;
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wire serial_data_in_available;
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wire [7:0] serial_data_in_cpu;
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wire serial_data_in_empty;
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wire [3:0] serial_data_in_space;
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always @(negedge clk) begin
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serial_cpu_data_readD <= serial_cpu_data_read;
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// read on uart data register
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serial_cpu_data_read <= 1'b0;
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if(sel && ~ds && rw && (addr == 5'h17))
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serial_cpu_data_read <= 1'b1;
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end
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wire write = sel && ~ds && ~rw;
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// timer a/b is in pulse mode
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wire [1:0] pulse_mode;
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wire timera_done;
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wire [7:0] timera_dat_o;
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wire [3:0] timera_ctrl_o;
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mfp_timer timer_a (
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.CLK (clk),
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.XCLK_I (clk_ext),
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.RST (reset),
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.CTRL_I (din[4:0]),
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.CTRL_O (timera_ctrl_o),
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.CTRL_WE ((addr == 5'h0c) && write),
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.DAT_I (din),
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.DAT_O (timera_dat_o),
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.DAT_WE ((addr == 5'h0f) && write),
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.PULSE_MODE (pulse_mode[1]),
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.T_I (t_i[0] ^ ~aer[4]),
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.T_O_PULSE (timera_done)
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);
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wire timerb_done;
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wire [7:0] timerb_dat_o;
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wire [3:0] timerb_ctrl_o;
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mfp_timer timer_b (
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.CLK (clk),
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.XCLK_I (clk_ext),
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.RST (reset),
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.CTRL_I (din[4:0]),
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.CTRL_O (timerb_ctrl_o),
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.CTRL_WE ((addr == 5'h0d) && write),
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.DAT_I (din),
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.DAT_O (timerb_dat_o),
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.DAT_WE ((addr == 5'h10) && write),
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.PULSE_MODE (pulse_mode[0]),
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.T_I (t_i[1] ^ ~aer[3]),
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.T_O_PULSE (timerb_done)
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);
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wire timerc_done;
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wire [7:0] timerc_dat_o;
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wire [3:0] timerc_ctrl_o;
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mfp_timer timer_c (
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.CLK (clk),
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.XCLK_I (clk_ext),
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.RST (reset),
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.CTRL_I ({2'b00, din[6:4]}),
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.CTRL_O (timerc_ctrl_o),
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.CTRL_WE ((addr == 5'h0e) && write),
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.DAT_I (din),
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.DAT_O (timerc_dat_o),
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.DAT_WE ((addr == 5'h11) && write),
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.T_O_PULSE (timerc_done)
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);
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wire timerd_done;
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wire [7:0] timerd_dat_o;
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wire [3:0] timerd_ctrl_o;
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wire [7:0] timerd_set_data;
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mfp_timer timer_d (
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.CLK (clk),
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.XCLK_I (clk_ext),
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.RST (reset),
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.CTRL_I ({2'b00, din[2:0]}),
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.CTRL_O (timerd_ctrl_o),
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.CTRL_WE ((addr == 5'h0e) && write),
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.DAT_I (din),
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.DAT_O (timerd_dat_o),
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.DAT_WE ((addr == 5'h12) && write),
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.T_O_PULSE (timerd_done),
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.SET_DATA_OUT (timerd_set_data)
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);
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reg [7:0] aer, ddr, gpip;
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// the mfp can handle 16 irqs, 8 internal and 8 external
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reg [15:0] imr, ier; // interrupt registers
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reg [7:0] vr;
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// generate irq signal if an irq is pending and no other irq of same or higher prio is in service
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assign irq = ((ipr & imr) != 16'h0000) && (highest_irq_pending > irq_in_service);
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// check number of current interrupt in service
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wire [3:0] irq_in_service;
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mfp_hbit16 irq_in_service_index (
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.value ( isr ),
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.index ( irq_in_service )
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);
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// check the number of the highest pending irq
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wire [3:0] highest_irq_pending;
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wire [15:0] highest_irq_pending_mask;
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mfp_hbit16 irq_pending_index (
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.value ( ipr & imr ),
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.index ( highest_irq_pending ),
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.mask ( highest_irq_pending_mask )
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);
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// gpip as output to the cpu (ddr bit == 1 -> gpip pin is output)
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wire [7:0] gpip_cpu_out = (i & ~ddr) | (gpip & ddr);
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// assemble output status structure. Adjust bitrate endianess
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assign serial_status_out = {
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bitrate[7:0], bitrate[15:8], bitrate[23:16], bitrate[31:24],
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databits, parity, stopbits, input_fifo_status };
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wire [11:0] timerd_state = { timerd_ctrl_o, timerd_set_data };
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// Atari RTS: YM-A-4 ->
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// Atari CTS: mfp gpio-2 <-
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// --- export bit rate ---
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// try to calculate bitrate from timer d config
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// bps is 2.457MHz/2/16/prescaler/datavalue
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wire [31:0] bitrate =
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(uart_ctrl[6] != 1'b1)?32'h80000000: // uart prescaler not 1
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(timerd_state == 12'h101)?32'd19200: // 19200 bit/s
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(timerd_state == 12'h102)?32'd9600: // 9600 bit/s
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(timerd_state == 12'h104)?32'd4800: // 4800 bit/s
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(timerd_state == 12'h105)?32'd3600: // 3600 bit/s (?? isn't that 3840?)
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(timerd_state == 12'h108)?32'd2400: // 2400 bit/s
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(timerd_state == 12'h10a)?32'd2000: // 2000 bit/s (exact 1920)
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(timerd_state == 12'h10b)?32'd1800: // 1800 bit/s (exact 1745)
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(timerd_state == 12'h110)?32'd1200: // 1200 bit/s
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(timerd_state == 12'h120)?32'd600: // 600 bit/s
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(timerd_state == 12'h140)?32'd300: // 300 bit/s
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(timerd_state == 12'h160)?32'd200: // 200 bit/s
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(timerd_state == 12'h180)?32'd150: // 150 bit/s
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(timerd_state == 12'h18f)?32'd134: // 134 bit/s
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(timerd_state == 12'h18f)?32'd134: // 134 bit/s (134.27)
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(timerd_state == 12'h1af)?32'd110: // 110 bit/s (109.71)
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(timerd_state == 12'h240)?32'd75: // 75 bit/s (120)
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(timerd_state == 12'h260)?32'd50: // 50 bit/s (80)
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32'h80000001; // unsupported bit rate
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wire [7:0] input_fifo_status = { serial_data_in_space, 1'b0,
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serial_data_in_empty, serial_data_in_full, serial_data_in_available };
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wire [7:0] parity =
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(uart_ctrl[1] == 1'b0)?8'h00: // no parity
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(uart_ctrl[0] == 1'b0)?8'h01: // odd parity
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8'h02; // even parity
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wire [7:0] stopbits =
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(uart_ctrl[3:2] == 2'b00)?8'hff: // sync mode not supported
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(uart_ctrl[3:2] == 2'b01)?8'h00: // async 1 stop bit
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(uart_ctrl[3:2] == 2'b10)?8'h01: // async 1.5 stop bits
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8'h11; // async 2 stop bits
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wire [7:0] databits =
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(uart_ctrl[5:4] == 2'b00)?8'd8: // 8 data bits
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(uart_ctrl[5:4] == 2'b01)?8'd7: // 7 data bits
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(uart_ctrl[5:4] == 2'b10)?8'd6: // 6 data bits
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8'd5; // 5 data bits
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// cpu controllable uart control bits
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reg [1:0] uart_rx_ctrl;
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reg [3:0] uart_tx_ctrl;
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reg [6:0] uart_ctrl;
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reg [7:0] uart_sync_chr;
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// cpu read interface
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always @(iack, sel, ds, rw, addr, gpip_cpu_out, aer, ddr, ier, ipr, isr, imr,
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vr, serial_data_out_fifo_full, timera_dat_o, timerb_dat_o,
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timerc_dat_o, timerd_dat_o, timera_ctrl_o, timerb_ctrl_o, timerc_ctrl_o,
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timerd_ctrl_o) begin
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dout = 8'd0;
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if(sel && ~ds && rw) begin
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if(addr == 5'h00) dout = gpip_cpu_out;
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if(addr == 5'h01) dout = aer;
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if(addr == 5'h02) dout = ddr;
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if(addr == 5'h03) dout = ier[15:8];
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if(addr == 5'h04) dout = ier[7:0];
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if(addr == 5'h06) dout = ipr[7:0];
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if(addr == 5'h05) dout = ipr[15:8];
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if(addr == 5'h07) dout = isr[15:8];
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if(addr == 5'h08) dout = isr[7:0];
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if(addr == 5'h09) dout = imr[15:8];
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if(addr == 5'h0a) dout = imr[7:0];
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if(addr == 5'h0b) dout = vr;
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// timers
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if(addr == 5'h0c) dout = { 4'h0, timera_ctrl_o};
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if(addr == 5'h0d) dout = { 4'h0, timerb_ctrl_o};
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if(addr == 5'h0e) dout = { timerc_ctrl_o, timerd_ctrl_o};
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if(addr == 5'h0f) dout = timera_dat_o;
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if(addr == 5'h10) dout = timerb_dat_o;
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if(addr == 5'h11) dout = timerc_dat_o;
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if(addr == 5'h12) dout = timerd_dat_o;
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// uart: report "tx buffer empty" if fifo is not full
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if(addr == 5'h13) dout = uart_sync_chr;
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if(addr == 5'h14) dout = { uart_ctrl, 1'b0 };
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if(addr == 5'h15) dout = { serial_data_in_available, 5'b00000 , uart_rx_ctrl};
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if(addr == 5'h16) dout = { !serial_data_out_fifo_full, 3'b000 , uart_tx_ctrl};
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if(addr == 5'h17) dout = serial_data_in_cpu;
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end else if(iack) begin
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dout = irq_vec;
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end
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end
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// mask of input irqs which are overwritten by timer a/b inputs
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wire [7:0] ti_irq_mask = { 3'b000, pulse_mode, 3'b000};
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wire [7:0] ti_irq = { 3'b000, t_i[0], t_i[1], 3'b000};
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// latch to keep irq vector stable during irq ack cycle
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reg [7:0] irq_vec;
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// IPR bits are always set on the rising edge of their input and are cleared asynchronously
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wire [7:0] gpio_irq = ~aer ^ ((i & ~ti_irq_mask) | (ti_irq & ti_irq_mask));
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// ------------------------ IPR register --------------------------
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wire [15:0] ipr;
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reg [15:0] ipr_reset;
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// the cpu reading data clears rx irq. It may raise again immediately if there's more
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// data in the input fifo. Use a delayed cpu read signal to make sure the fifo finishes
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// removing the byte before
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wire uart_rx_irq = serial_data_in_available && !serial_cpu_data_readD;
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// the io controller reading data clears tx irq. It may raus again immediately if
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// there's more data in the output fifo
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wire uart_tx_irq = !serial_data_out_fifo_full && !serial_strobe_out;
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// map the 16 interrupt sources onto the 16 interrupt register bits
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wire [15:0] ipr_set = {
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gpio_irq[7:6], timera_done, uart_rx_irq,
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1'b0 /* rcv err */, uart_tx_irq, 1'b0 /* tx err */, timerb_done,
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gpio_irq[5:4], timerc_done, timerd_done, gpio_irq[3:0]
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};
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mfp_srff16 ipr_latch (
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.set ( ipr_set ),
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.mask ( ier ),
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.reset ( ipr_reset ),
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.out ( ipr )
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);
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// ------------------------ ISR register --------------------------
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wire [15:0] isr;
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reg [15:0] isr_reset;
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reg [15:0] isr_set;
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// move highest pending irq into isr when s bit set and iack raises
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mfp_srff16 isr_latch (
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.set ( isr_set ),
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.mask ( 16'hffff ),
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.reset ( isr_reset ),
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.out ( isr )
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);
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// this needs to happen at the same time the isr is set so it doesn't hurt
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// if a new irq arrives in between these two events and a different irq is
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// moved from ipr to isr than reported to the cpu
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always @(posedge iack)
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irq_vec <= { vr[7:4], highest_irq_pending };
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always @(negedge clk) begin
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ipr_reset <= 16'h0000;
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isr_reset <= 16'h0000;
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if(reset) begin
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ipr_reset <= 16'hffff;
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isr_reset <= 16'hffff;
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ier <= 16'h0000;
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imr <= 16'h0000;
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isr_set <= 16'h0000;
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end else begin
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// remove active bit from ipr and set it in isr
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if(iack) begin
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ipr_reset[highest_irq_pending] <= 1'b1;
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isr_set <= (vr[3] && iack)?highest_irq_pending_mask:16'h0000;
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end
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if(sel && ~ds && ~rw) begin
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// -------- GPIO ---------
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if(addr == 5'h00) gpip <= din;
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if(addr == 5'h01) aer <= din;
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if(addr == 5'h02) ddr <= din;
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// ------ IRQ handling -------
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if(addr == 5'h03) begin
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ier[15:8] <= din;
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ipr_reset[15:8] <= ipr_reset[15:8] | ~din;
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end
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if(addr == 5'h04) begin
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ier[7:0] <= din;
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ipr_reset[7:0] <= ipr_reset[7:0] | ~din;
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end
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if(addr == 5'h05) ipr_reset[15:8] <= ipr_reset[15:8] | ~din;
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if(addr == 5'h06) ipr_reset[7:0] <= ipr_reset[7:0] | ~din;
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if(addr == 5'h07) isr_reset[15:8] <= isr_reset[15:8] | ~din; // zero bits are cleared
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if(addr == 5'h08) isr_reset[7:0] <= isr_reset[7:0] | ~din; // -"-
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if(addr == 5'h09) imr[15:8] <= din;
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if(addr == 5'h0a) imr[7:0] <= din;
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if(addr == 5'h0b) vr <= din;
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// ------- uart ------------
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if(addr == 5'h13) uart_sync_chr <= din[1:0];
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if(addr == 5'h14) uart_ctrl <= din[7:1];
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if(addr == 5'h15) uart_rx_ctrl <= din[1:0];
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if(addr == 5'h16) uart_tx_ctrl <= din[3:0];
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// write to addr == 5'h17 is handled by the output fifo
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end
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end
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end
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endmodule
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