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180 lines
6.5 KiB
Verilog
180 lines
6.5 KiB
Verilog
//
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// sdram.v
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//
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// sdram controller implementation for the MiST board adaptation
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// of Luddes NES core
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module sdram (
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// interface to the MT48LC16M16 chip
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inout reg [15:0] sd_data, // 16 bit bidirectional data bus
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output reg [12:0] sd_addr, // 13 bit multiplexed address bus
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output reg [1:0] sd_dqm, // two byte masks
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output reg [1:0] sd_ba, // two banks
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output reg sd_cs, // a single chip select
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output reg sd_we, // write enable
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output reg sd_ras, // row address select
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output reg sd_cas, // columns address select
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// cpu/chipset interface
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input init, // init signal after FPGA config to initialize RAM
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input clk, // sdram is accessed at up to 128MHz
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input clkref, // reference clock to sync to
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input [24:0] addrA, // 25 bit byte address
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input weA, // cpu/chipset requests write
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input [7:0] dinA, // data input from chipset/cpu
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input oeA, // cpu requests data
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output reg [7:0] doutA, // data output to cpu
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input [24:0] addrB, // 25 bit byte address
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input weB, // cpu/chipset requests write
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input [7:0] dinB, // data input from chipset/cpu
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input oeB, // ppu requests data
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output reg [7:0] doutB // data output to ppu
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);
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// no burst configured
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localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@85MHz
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localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
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localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
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localparam CAS_LATENCY = 3'd2; // 2/3 allowed
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localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
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localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
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localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
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// ---------------------------------------------------------------------
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// ------------------------ cycle state machine ------------------------
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// ---------------------------------------------------------------------
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localparam STATE_FIRST = 3'd0; // first state in cycle
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localparam STATE_CMD_START = 3'd1; // state in which a new command can be started
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localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY; // 3 command can be continued
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localparam STATE_CMD_READ = STATE_CMD_CONT + CAS_LATENCY + 1'd1; // 6 read state
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localparam STATE_LAST = 3'd7; // last state in cycle
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reg [2:0] q;
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always @(posedge clk) begin
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// SDRAM (state machine) clock is 85MHz. Synchronize this to systems 21.477 Mhz clock
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// force counter to pass state LAST->FIRST exactly after the rising edge of clkref
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reg clkref_last;
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clkref_last <= clkref;
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q <= q + 1'd1;
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if (q==STATE_LAST) q<=STATE_FIRST;
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if (~clkref_last & clkref) q<=STATE_FIRST + 1'd1;
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end
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// ---------------------------------------------------------------------
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// --------------------------- startup/reset ---------------------------
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// ---------------------------------------------------------------------
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// wait 1ms (85000 cycles) after FPGA config is done before going
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// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
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reg [16:0] reset;
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always @(posedge clk) begin
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if(init) reset <= 17'h14c08;
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else if((q == STATE_LAST) && (reset != 0))
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reset <= reset - 17'd1;
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end
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// ---------------------------------------------------------------------
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// ------------------ generate ram control signals ---------------------
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// ---------------------------------------------------------------------
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// all possible commands
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localparam CMD_INHIBIT = 4'b1111;
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localparam CMD_NOP = 4'b0111;
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localparam CMD_ACTIVE = 4'b0011;
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localparam CMD_READ = 4'b0101;
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localparam CMD_WRITE = 4'b0100;
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localparam CMD_BURST_TERMINATE = 4'b0110;
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localparam CMD_PRECHARGE = 4'b0010;
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localparam CMD_AUTO_REFRESH = 4'b0001;
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localparam CMD_LOAD_MODE = 4'b0000;
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wire [3:0] sd_cmd; // current command sent to sd ram
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// clkref high - CPU
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// clkref low - PPU
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wire oe = clkref ? oeA : oeB;
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wire we = clkref ? weA : weB;
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wire [24:0] addr = clkref ? addrA : addrB;
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wire [7:0] din = clkref ? dinA : dinB;
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reg addr0;
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always @(posedge clk)
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if((q == 1) && oe) addr0 <= addr[0];
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wire [7:0] dout = addr0?sd_data[7:0]:sd_data[15:8];
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always @(posedge clk) begin
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if(q == STATE_CMD_READ) begin
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if(oeA && clkref) doutA <= dout;
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if(oeB && !clkref) doutB <= dout;
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end
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end
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wire [3:0] reset_cmd =
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((q == STATE_CMD_START) && (reset == 13))?CMD_PRECHARGE:
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((q == STATE_CMD_START) && (reset == 2))?CMD_LOAD_MODE:
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CMD_INHIBIT;
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wire [3:0] run_cmd =
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((we || oe) && (q == STATE_CMD_START))?CMD_ACTIVE:
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( we && (q == STATE_CMD_CONT ))?CMD_WRITE:
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(!we && oe && (q == STATE_CMD_CONT ))?CMD_READ:
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(!we && !oe && (q == STATE_CMD_START))?CMD_AUTO_REFRESH:
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CMD_INHIBIT;
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assign sd_cmd = (reset != 0)?reset_cmd:run_cmd;
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wire [12:0] reset_addr = (reset == 13)?13'b0010000000000:MODE;
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wire [12:0] run_addr =
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(q == STATE_CMD_START)?addr[21:9]:{ 4'b0010, addr[24], addr[8:1]};
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//register SDRAM output signals
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always @(posedge clk) begin
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// drive ram data lines when writing, set them as inputs otherwise
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// the eight bits are sent on both bytes ports. Which one's actually
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// written depends on the state of dqm of which only one is active
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// at a time when writing
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sd_data <= we?{ din, din }:16'bZZZZZZZZZZZZZZZZ;
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sd_addr <= (reset != 0)?reset_addr:run_addr;
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sd_ba <= (reset != 0)?2'b00:addr[23:22];
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sd_dqm <= we?{ addr[0], ~addr[0] }:2'b00;
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// drive control signals according to current command
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sd_cs <= sd_cmd[3];
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sd_ras <= sd_cmd[2];
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sd_cas <= sd_cmd[1];
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sd_we <= sd_cmd[0];
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end
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endmodule
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