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27 lines
701 B
Verilog
27 lines
701 B
Verilog
module videoShifter(
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input clk32,
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input [1:0] clkPhase,
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input [15:0] dataIn,
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input loadPixels,
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output pixelOut
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);
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reg [15:0] shiftRegister;
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// a 0 bit is white, and a 1 bit is black
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// data is shifted out MSB first
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assign pixelOut = ~shiftRegister[15];
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always @(posedge clk32) begin
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// loadPixels is generated by a module running on the 8 MHz CPU clock. Therefore this module
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// only honors loadPixels when clkPhase is 1, indicating the last quarter of the 8 MHz clock cycle.
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if (loadPixels && clkPhase == 2'b01) begin
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shiftRegister <= dataIn;
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end
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else begin
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shiftRegister <= { shiftRegister[14:0], 1'b1 };
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end
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end
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endmodule
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