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118 lines
3.3 KiB
Verilog
118 lines
3.3 KiB
Verilog
//
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// ipc.v
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//
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// Sinclair QL for the MiST
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// https://github.com/mist-devel
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//
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// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module ipc (
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input reset,
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input clk_sys,
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// synchronous serial connection
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output comctrl,
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input comdata_in,
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output comdata_out,
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output audio,
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output [1:0] ipl,
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input [4:0] js0,
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input [4:0] js1,
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input ps2_kbd_clk,
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input ps2_kbd_data
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);
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// ---------------------------------------------------------------------------------
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// -------------------------------------- KBD --------------------------------------
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// ---------------------------------------------------------------------------------
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wire [63:0] kbd_matrix;
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keyboard keyboard (
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.reset ( reset ),
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.clk ( clk11 ),
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.ps2_clk ( ps2_kbd_clk ),
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.ps2_data ( ps2_kbd_data ),
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.js0 ( js0 ),
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.js1 ( js1 ),
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.matrix ( kbd_matrix )
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);
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// ---------------------------------------------------------------------------------
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// ----------------------------------- 8049 clock ----------------------------------
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// ---------------------------------------------------------------------------------
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wire clk11;
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wire pll_locked;
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pll_ipc pll_ipc (
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.inclk0 ( clk_sys ),
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.locked ( pll_locked ),
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.c0 ( clk11 ) // 11 MHz
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);
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// make sure IPC clock is stable before it starts
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wire ipc_reset = reset || !pll_locked;
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// ---------------------------------------------------------------------------------
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// -------------------------------------- 8049 -------------------------------------
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// ---------------------------------------------------------------------------------
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assign audio = t8049_p2_o[1];
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assign ipl = t8049_p2_o[3:2];
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wire [7:0] t8049_p1_o;
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wire [7:0] t8049_db_i;
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wire [7:0] t8049_p2_o;
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wire [7:0] t8049_p2_i = { comdata_out && comdata_in, 7'b0000000 };
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assign comdata_out = t8049_p2_o[7];
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t8049_notri #(0) t8049 (
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.xtal_i ( clk11 ),
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.xtal_en_i ( 1'b1 ),
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.reset_n_i ( !ipc_reset ),
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.t0_i ( 1'b0 ),
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.t1_i ( 1'b0 ),
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.int_n_i ( 1'b1 ),
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.wr_n_o ( comctrl ),
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.ea_i ( 1'b0 ),
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.db_i ( t8049_db_i ),
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.p1_i ( 8'h00 ),
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.p1_o ( t8049_p1_o ),
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.p2_i ( t8049_p2_i ),
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.p2_o ( t8049_p2_o )
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);
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assign t8049_db_i =
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(t8049_p1_o[0]?kbd_matrix[ 7: 0]:8'h00)|
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(t8049_p1_o[1]?kbd_matrix[15: 8]:8'h00)|
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(t8049_p1_o[2]?kbd_matrix[23:16]:8'h00)|
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(t8049_p1_o[3]?kbd_matrix[31:24]:8'h00)|
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(t8049_p1_o[4]?kbd_matrix[39:32]:8'h00)|
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(t8049_p1_o[5]?kbd_matrix[47:40]:8'h00)|
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(t8049_p1_o[6]?kbd_matrix[55:48]:8'h00)|
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(t8049_p1_o[7]?kbd_matrix[63:56]:8'h00);
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endmodule
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