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104 lines
2.1 KiB
Verilog
104 lines
2.1 KiB
Verilog
// divmmc
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module divmmc (
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input reset_n,
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input clk,
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input clken,
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// Bus interface
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input enable,
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input [15:0] a,
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input wr_n,
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input rd_n,
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input mreq_n,
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input m1_n,
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input [7:0] din,
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output [7:0] dout,
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// memory state
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output reg paged_in,
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output [3:0] sram_page,
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output mapram,
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output conmem,
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// SD card interface
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output reg sd_cs,
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output sd_sck,
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output sd_mosi,
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input sd_miso
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);
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reg m1_trigger;
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assign sram_page = ctrl[3:0];
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assign mapram = ctrl[6];
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assign conmem = ctrl[7];
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reg [7:0] ctrl;
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// Control del modulo SPI
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reg spi_tx_strobe;
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reg spi_rx_strobe;
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reg [7:0] acc_cnt /* synthesis noprune */;
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always @(posedge enable or negedge reset_n) begin
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if(reset_n == 1'b0)
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acc_cnt <= 8'd0;
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else
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acc_cnt <= acc_cnt + 8'd1;
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end
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always @(posedge clk) begin
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if(reset_n == 1'b0) begin
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m1_trigger <= 1'b0;
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paged_in <= 1'b0;
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ctrl <= 8'h00;
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sd_cs <= 1'b1;
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end else begin
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spi_rx_strobe = 1'b0;
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spi_tx_strobe = 1'b0;
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if (a[3:0]==4'h3 && enable && !wr_n)
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ctrl <= din;
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if(a[3:0]==4'h7 && enable && !wr_n)
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sd_cs <= din[0];
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// SPI read/write
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if(enable && a[3:0]==4'hb) begin
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if(wr_n) spi_rx_strobe = 1'b1;
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else spi_tx_strobe = 1'b1;
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end
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if (!mreq_n && !rd_n && !m1_n &&
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((a==16'h0000) || (a==16'h0008) || (a==16'h0038) ||
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(a==16'h0066) || (a==16'h04C6) || (a==16'h0562))) begin
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// activate automapper after this cycle
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m1_trigger <= 1'b1;
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end else if (!mreq_n && !rd_n && !m1_n && a[15:8]==8'h3D) begin
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// activate automapper immediately
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paged_in <= 1'b1;
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m1_trigger <= 1'b1;
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end else if (!mreq_n && !rd_n && !m1_n && {a[15:3],3'd0} == 16'h1ff8) begin
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// deactivate automapper after this cycle
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m1_trigger <= 1'b0;
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end
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if (m1_n==1'b1)
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paged_in <= m1_trigger;
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end
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end
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spi mi_spi (
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.clk(clk),
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.tx_strobe(spi_tx_strobe),
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.rx_strobe(spi_rx_strobe),
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.din(din),
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.dout(dout),
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.spi_clk(sd_sck),
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.spi_di(sd_miso),
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.spi_do(sd_mosi)
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);
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endmodule
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