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36 lines
1.0 KiB
Verilog
36 lines
1.0 KiB
Verilog
// spi.v inspired by zxuno project
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module spi (
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input clk, // 7MHz
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input tx_strobe, // Byte ready to be transmitted
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input rx_strobe, // request to read one byte
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input [7:0] din, // del bus de datos de salida de la CPU
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output reg [7:0] dout, // al bus de datos de entrada de la CPU
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output spi_clk, // spi itself
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input spi_di, //
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output spi_do //
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);
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reg [4:0] counter = 5'd16; // tx/rx counter is idle
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reg [7:0] io_byte;
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assign spi_clk = counter[0];
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assign spi_do = io_byte[7]; // data is shifted up during transfer
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wire io_strobe = tx_strobe || rx_strobe;
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always @(posedge clk) begin
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// spi engine idle and is supposed to be started?
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if (io_strobe && (counter == 16)) begin
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// kickstart engine
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counter <= 5'd0;
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dout <= io_byte;
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io_byte <= tx_strobe?din:8'hff;
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end else if(counter != 16) begin
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if(spi_clk) io_byte <= { io_byte[6:0], spi_di };
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counter <= counter + 5'd1;
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end
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end
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endmodule
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