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138 lines
3.6 KiB
Verilog
138 lines
3.6 KiB
Verilog
//
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// tape.v
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//
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// tape implementation for the spectrum core for the MiST board
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// http://code.google.com/p/mist-board/
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//
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// This reads a CSW1 file as described here:
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// http://ramsoft.bbk.org.omegahg.com/csw.html#CSW1FORMAT
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//
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// typical header:
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// 00000000 43 6f 6d 70 72 65 73 73 65 64 20 53 71 75 61 72 |Compressed Squar|
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// 00000010 65 20 57 61 76 65 1a 01 01 44 ac 01 00 00 00 00 |e Wave...D......|
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module tape #(parameter ADDR_WIDTH=16) (
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input reset,
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input clk,
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input iocycle,
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input downloading, // signal indicating an active download
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input [ADDR_WIDTH-1:0] size, // number of bytes in input buffer
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output reg audio_out,
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// external ram interface
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output rd,
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output [ADDR_WIDTH-1:0] a,
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input [7:0] d
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);
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reg downloadingD;
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reg [15:0] freq;
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reg [5:0] header_cnt;
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reg [31:0] clk_play_cnt;
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reg [ADDR_WIDTH-1:0] payload_cnt;
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reg iocycleD;
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reg [31:0] bit_cnt;
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reg [2:0] reload32;
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assign rd = iocycle && ((header_cnt != 0) || (payload_cnt != 0));
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assign a = (header_cnt != 0)?(25'h200000 + 25'd32 - header_cnt):
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(payload_cnt != 0)?(25'h200000 + size - payload_cnt):
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25'h12345;
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reg [7:0] din;
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// latch data at end of io cycle
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always @(negedge iocycle)
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din <= d;
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always @(posedge clk) begin
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downloadingD <= downloading;
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iocycleD <= iocycle;
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if(reset || downloading) begin
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freq <= 16'd1234;
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header_cnt <= 6'd0;
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payload_cnt <= 25'd0;
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reload32 <= 3'd0;
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end else begin
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// download complete, start parsing
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if(!downloading && downloadingD)
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header_cnt <= 6'd32;
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// read header
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if((header_cnt != 0) && !iocycle && iocycleD ) begin
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// fetch playback frequency from header
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if(header_cnt == 6'h20 - 6'h19) freq[ 7:0] <= din;
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if(header_cnt == 6'h20 - 6'h1a) freq[15:8] <= din;
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header_cnt <= header_cnt - 6'd1;
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// start payload transfer as soon as header has been parsed
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if(header_cnt == 1) begin
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payload_cnt <= size - 25'h20;
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bit_cnt <= 32'd1;
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end
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end
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// read payload
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if(payload_cnt != 0) begin
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// bit has fully neem semt or reload32 in progress
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if((bit_cnt <= 1) || (reload32 != 0)) begin
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if(!iocycle && iocycleD ) begin
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if(reload32 != 0) begin
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bit_cnt <= { din, bit_cnt[31:8] };
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reload32 <= reload32 - 3'd1;
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end else begin
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if(din != 0) begin
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// determine length of next bit
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bit_cnt <= { 24'd0, din};
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end else
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reload32 <= 3'd4;
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// output a bit ...
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audio_out <= !audio_out;
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end
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payload_cnt <= payload_cnt - 25'd1;
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end
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end else begin
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// generate replay clock
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clk_play_cnt <= clk_play_cnt + { 16'h0000, freq};
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// clock is 28MHz
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if(clk_play_cnt > 32'd28000000) begin
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clk_play_cnt <= clk_play_cnt - 32'd28000000;
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// process bit counter
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bit_cnt <= bit_cnt - 32'd1;
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end
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end
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end
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end
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end
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endmodule
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