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80 lines
2.2 KiB
Verilog
80 lines
2.2 KiB
Verilog
// A simple pong game for the MIST FPGA board
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// (c) 2015 Till Harbaum
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// Lesson 1: VGA signal with ball
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module pong (
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input [1:0] CLOCK_27,
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output SDRAM_nCS,
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output reg VGA_HS,
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output reg VGA_VS,
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B
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);
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// 640x480 60HZ VESA laut http://tinyvga.com/vga-timing/640x480@60Hz
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parameter H = 640; // width of visible area
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parameter HFP = 16; // unused area before h sync
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parameter HS = 96; // length of h sync
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parameter HBP = 48; // unused area after h sync
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parameter V = 480; // height of visible area
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parameter VFP = 10; // unused area before v sync
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parameter VS = 2; // length of v sync
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parameter VBP = 33; // unused area after v sync
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reg[9:0] h_cnt; // horizontal pixel counter
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reg[9:0] v_cnt; // vertical pixel counter
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// deactivate unused sdram
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assign SDRAM_nCS = 1;
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localparam BALL_SIZE = 16; // width and height of ball
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// ball starts in center of visible area
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reg [9:0] ball_x = HS + HBP + (H - BALL_SIZE)/2;
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reg [9:0] ball_y = VS + VBP + (V - BALL_SIZE)/2;
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// both counters start with the begin of the sync phases
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// horizontal pixel counter
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always@(posedge pixel_clock) begin
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if(h_cnt==HS+HBP+H+HFP-1) h_cnt <= 0;
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else h_cnt <= h_cnt + 1;
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// generation of the negative h sync signal
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VGA_HS <= (h_cnt >= HS);
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end
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// vertical pixel counter
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always@(posedge pixel_clock) begin
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// the vertical state changes at the begin of each line
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if(h_cnt == 0) begin
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if(v_cnt==VS+VBP+V+VFP-1) v_cnt <= 0;
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else v_cnt <= v_cnt + 1;
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// generation of the negative v sync signal
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VGA_VS <= (v_cnt >= VS);
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end
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end
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// signal indicating the presence of the ball at the current beam position
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wire ball = (h_cnt >= ball_x) && (h_cnt < ball_x + BALL_SIZE) &&
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(v_cnt >= ball_y) && (v_cnt < ball_y + BALL_SIZE);
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wire pixel = ball;
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// white if pixel, black otherwise
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assign VGA_R = pixel?6'b111111:6'b000000;
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assign VGA_G = pixel?6'b111111:6'b000000;
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assign VGA_B = pixel?6'b111111:6'b000000;
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// pll to generate the VGA pixel clock from the 27Mhz board clock
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pll pll (
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.inclk0(CLOCK_27[0]),
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.c0(pixel_clock)
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);
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endmodule
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