From 9a71dfd28f247e099f5fe3d067cccadcb0914939 Mon Sep 17 00:00:00 2001 From: Emard Date: Tue, 18 Oct 2016 01:53:16 +0200 Subject: [PATCH] esa11: fpga.c fix -> leave SPI lines in useable state for user_io.c and for xilinx load default bitstream X7A102T.BIN --- fpga.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fpga.c b/fpga.c index 817103d..3c02d9d 100644 --- a/fpga.c +++ b/fpga.c @@ -155,7 +155,7 @@ RAMFUNC unsigned char ConfigureFpga(char *name) if(!name) // name = "CORE BIN"; - name = "XESM38 BIN"; + name = "X7A102T BIN"; // open bitstream file if (FileOpen(&file, name) == 0) @@ -209,8 +209,8 @@ RAMFUNC unsigned char ConfigureFpga(char *name) } while (t < n); - // disable outputs - *AT91C_PIOA_ODR = XILINX_CCLK | XILINX_DIN | XILINX_PROG_B; + // return outputs to a state suitable for user_io.c + *AT91C_PIOA_SODR = XILINX_CCLK | XILINX_DIN | XILINX_PROG_B; iprintf("]\r"); iprintf("FPGA bitstream loaded\r");