mirror of
https://github.com/mist-devel/mist-firmware.git
synced 2026-04-19 08:49:40 +00:00
199 lines
5.8 KiB
C
199 lines
5.8 KiB
C
/*
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This file is part of MiST-firmware
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MiST-firmware is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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MiST-firmware is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _HARDWARE_H_
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#define _HARDWARE_H_
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#include "chip.h"
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#include "samv71.h"
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#include "core_cm7.h"
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#define MCLK 144000000
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#define PLLCLK 288000000
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#define FWS 6
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#define FLASH_PAGESIZE 512
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#define DMA_CH_MMC 0
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#define DMA_CH_SPI_TRANS 1
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#define DMA_CH_SPI_REC 2
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#define DMA_CH_QSPI_TRANS 3
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#define DMA_CH_QSPI_REC 4
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#define DISKLED PIO_PD28
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#define DISKLED_ON PIOD->PIO_CODR = DISKLED;
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#define DISKLED_OFF PIOD->PIO_SODR = DISKLED;
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#define USB_SEL PIO_PD25
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#define USB_INT PIO_PD24
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// fpga programming interface
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#define FPGA_OER PIOD->PIO_OER
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#define FPGA_SODR PIOD->PIO_SODR
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#define FPGA_CODR PIOD->PIO_CODR
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#define FPGA_PDSR PIOD->PIO_PDSR
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#define FPGA_DONE_PDSR PIOD->PIO_PDSR
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#define FPGA_DONE_SODR PIOD->PIO_SODR
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#define FPGA_DONE_CODR PIOD->PIO_CODR
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#define FPGA_DATA0_SODR PIOD->PIO_SODR
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#define FPGA_DATA0_CODR PIOD->PIO_CODR
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#ifdef EMIST
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// xilinx programming interface
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#define XILINX_DONE PIO_PB13
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#define XILINX_DIN PIO_PD12
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#define XILINX_INIT_B PIO_PA8
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#define XILINX_PROG_B PIO_PA7
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#define XILINX_CCLK PIO_PA15
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#else
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// altera programming interface
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#define ALTERA_DONE PIO_PD17
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#define ALTERA_DATA0 PIO_PD12
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#define ALTERA_NCONFIG PIO_PD14
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#define ALTERA_NSTATUS PIO_PD16
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#define ALTERA_DCLK PIO_PD13
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#define ALTERA_START_CONFIG PIOD->PIO_PER = ALTERA_DATA0;
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#define ALTERA_STOP_CONFIG PIOD->PIO_PDR = ALTERA_DATA0;
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#define ALTERA_NCONFIG_SET PIOD->PIO_ODR = ALTERA_NCONFIG; PIOD->PIO_PUER = ALTERA_NCONFIG;
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#define ALTERA_NCONFIG_RESET PIOD->PIO_PUDR = ALTERA_NCONFIG; PIOD->PIO_CODR = ALTERA_NCONFIG; PIOD->PIO_OER = ALTERA_NCONFIG;
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#define ALTERA_DCLK_SET PIOD->PIO_SODR = ALTERA_DCLK
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#define ALTERA_DCLK_RESET PIOD->PIO_CODR = ALTERA_DCLK
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#define ALTERA_DATA0_SET PIOD->PIO_SODR = ALTERA_DATA0;
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#define ALTERA_DATA0_RESET PIOD->PIO_CODR = ALTERA_DATA0;
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#define ALTERA_NSTATUS_STATE (PIOD->PIO_PDSR & ALTERA_NSTATUS)
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#define ALTERA_DONE_STATE (PIOD->PIO_PDSR & ALTERA_DONE)
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#endif
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// chip selects for FPGA communication
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#define FPGA0 PIO_PD27
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#define FPGA1 PIO_PB2
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#define FPGA3 PIO_PD12 // same as ALTERA_DATA0
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// SD
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#define SD_CD PIO_PD18
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#define SD_WP PIO_PD19
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// Buttons
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#define BTN_PORT PIOD
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#define BTN_RESET PIO_PD11
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#define BTN_OSD PIO_PD10
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#define SW1 PIO_PD30
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#define SW2 PIO_PD26
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// Joystick
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#define JOY0 (PIOA->PIO_PDSR & (JOY0_LEFT | JOY0_RIGHT | JOY0_UP | JOY0_DOWN | JOY0_BTN1 | JOY0_BTN2))
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#define JOY0_LEFT PIO_PA24
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#define JOY0_RIGHT PIO_PA8
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#define JOY0_UP PIO_PA23
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#define JOY0_DOWN PIO_PA5
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#define JOY0_BTN1 PIO_PA7
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#define JOY0_BTN2 PIO_PA15
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#define JOY0_SEL_PORT PIOB
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#define JOY0_SEL_PIN PIO_PB0
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#define JOY1 (PIOA->PIO_PDSR & (JOY1_LEFT | JOY1_RIGHT | JOY1_UP | JOY1_DOWN | JOY1_BTN1 | JOY1_BTN2))
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#define JOY1_LEFT PIO_PA2
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#define JOY1_RIGHT PIO_PA22
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#define JOY1_UP PIO_PA0
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#define JOY1_DOWN PIO_PA1
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#define JOY1_BTN1 PIO_PA21
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#define JOY1_BTN2 PIO_PA16
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#define JOY1_SEL_PORT PIOB
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#define JOY1_SEL_PIN PIO_PB1
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#define PHY_RESET PIO_PA18
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#define PHY_INT PIO_PA19
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#define PHY_SIGDET PIO_PA20
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// in non-cached RAM
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#define USB_LOAD_VAR *(int*)(0x2045F000)
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#define USB_LOAD_VALUE 0x12345678
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#define USB_BOOT_VALUE 0x8007F007
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#define USB_BOOT_VAR (*(int*)0x002045F013)
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#define DEBUG_MODE_VAR *(int*)(0x2045F008)
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#define DEBUG_MODE_VALUE 87654321
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#define DEBUG_MODE (DEBUG_MODE_VAR == DEBUG_MODE_VALUE)
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#define VIDEO_KEEP_VALUE 0x87654321
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#define VIDEO_KEEP_VAR (*(int*)0x2045F00C)
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#define VIDEO_ALTERED_VAR (*(uint8_t*)0x2045F010)
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#define VIDEO_SD_DISABLE_VAR (*(uint8_t*)0x2045F011)
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#define VIDEO_YPBPR_VAR (*(uint8_t*)0x2045F012)
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#define SECTOR_BUFFER_SIZE 8192
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void __init_hardware();
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char mmc_inserted();
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char mmc_write_protected();
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void USART_Init(unsigned long baudrate);
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void USART_Write(unsigned char c);
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unsigned char USART_Read();
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unsigned long CheckButton();
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void Timer_Init();
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unsigned long GetTimer(unsigned long offset);
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unsigned long CheckTimer(unsigned long t);
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void WaitTimer(unsigned long time);
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void USART_Poll();
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void MCUReset();
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void InitRTTC();
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int GetRTTC();
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int GetSPICLK();
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void InitADC();
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void PollADC();
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// user, menu, DIP2, DIP1
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unsigned char Buttons();
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unsigned char MenuButton();
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unsigned char UserButton();
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void InitDB9();
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char GetDB9(char index, uint16_t *joy_map);
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char GetRTC(unsigned char *d);
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char SetRTC(unsigned char *d);
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void UnlockFlash();
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void WriteFlash(unsigned long page);
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#ifdef FPGA3
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// the MiST has the user inout on the arm controller
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void EnableIO();
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void DisableIO();
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#endif
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#define DEBUG_FUNC_IN()
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#define DEBUG_FUNC_OUT()
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unsigned char CheckFirmware(char *name);
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void WriteFirmware(char *name);
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char *GetFirmwareVersion(char *name);
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#endif
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