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139 lines
4.0 KiB
C
139 lines
4.0 KiB
C
/* ----------------------------------------------------------------------------
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2015, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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#ifndef L1CACHE_H_
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#define L1CACHE_H_
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/*
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* Functions related to L1 cache maintenance (I-Cache and D-Cache).
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*
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* Actual implementation is located in arch/ since L1 is part of the CPU core.
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*/
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#ifdef CONFIG_HAVE_L1CACHE
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/*------------------------------------------------------------------------------
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* Headers
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*------------------------------------------------------------------------------*/
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#include <stdint.h>
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#include <stdbool.h>
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/*------------------------------------------------------------------------------
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* Exported functions
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*------------------------------------------------------------------------------*/
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/**
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* \brief Invalidate all instruction cache.
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*/
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extern void icache_invalidate(void);
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/**
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* \brief Check if instruction cache is enabled.
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*/
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extern bool icache_is_enabled(void);
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/**
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* \brief Enable instruction cache.
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*/
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extern void icache_enable(void);
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/**
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* \brief Disable instruction cache.
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*/
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extern void icache_disable(void);
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/**
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* \brief Check if data cache is enabled.
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*/
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extern bool dcache_is_enabled(void);
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/**
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* \brief Enable data cache.
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*/
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extern void dcache_enable(void);
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/**
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* \brief Disable the data cache.
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*/
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extern void dcache_disable(void);
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/**
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* \brief Clean the data cache.
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*/
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extern void dcache_clean(void);
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/**
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* \brief Invalidate the data cache.
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*/
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extern void dcache_invalidate(void);
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/**
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* \brief Clean & Invalidate the data cache.
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*/
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extern void dcache_clean_invalidate(void);
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/**
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* \brief Invalidate the data cache within the specified region
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* \param start virtual start address of region
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* \param end virtual end address of region
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*/
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extern void dcache_invalidate_region(uint32_t start, uint32_t end);
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/**
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* \brief Clean the data cache within the specified region.
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* \param start virtual start address of region
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* \param end virtual end address of region
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*/
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extern void dcache_clean_region(uint32_t start, uint32_t end);
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/**
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* \brief Clean and invalidate the data cache within the specified region.
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* \param start virtual start address of region
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* \param end virtual end address of region
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*/
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extern void dcache_clean_invalidate_region(uint32_t start, uint32_t end);
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/**
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* \brief Enable exclusive caching for the L1 cache.
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*
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* The L2 cache must also be configured in exclusive mode.
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*/
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extern void dcache_set_exclusive(void);
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/**
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* \brief Allow data to reside in the L1 and L2 caches at the same time.
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*/
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extern void dcache_set_non_exclusive(void);
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#endif /* CONFIG_HAVE_L1CACHE */
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#endif /* L1CACHE_H_ */
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