mirror of
https://github.com/mist-devel/mist-firmware.git
synced 2026-01-25 03:25:42 +00:00
337 lines
9.6 KiB
C
337 lines
9.6 KiB
C
/*
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Copyright 2008, 2009 Jakub Bednarski
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This file is part of Minimig
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Minimig is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Minimig is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <ctype.h>
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#include "AT91SAM7S256.h"
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#include "stdio.h"
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#include "hardware.h"
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#include "user_io.h"
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#include "xmodem.h"
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#include "ikbd.h"
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uint8_t rstval = 0;
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void __init_hardware(void)
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{
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*AT91C_WDTC_WDMR = AT91C_WDTC_WDDIS; // disable watchdog
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*AT91C_RSTC_RMR = (0xA5 << 24) | AT91C_RSTC_URSTEN; // enable external user reset input
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*AT91C_MC_FMR = FWS << 8; // Flash wait states
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// configure clock generator
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*AT91C_CKGR_MOR = AT91C_CKGR_MOSCEN | (40 << 8);
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while (!(*AT91C_PMC_SR & AT91C_PMC_MOSCS));
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*AT91C_CKGR_PLLR = AT91C_CKGR_OUT_0 | AT91C_CKGR_USBDIV_1 | (25 << 16) | (40 << 8) | 5; // DIV=5 MUL=26 USBDIV=1 (2) PLLCOUNT=40
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while (!(*AT91C_PMC_SR & AT91C_PMC_LOCK));
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*AT91C_PMC_MCKR = AT91C_PMC_PRES_CLK_2; // master clock register: clock source selection
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while (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY));
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*AT91C_PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2; // master clock register: clock source selection
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while (!(*AT91C_PMC_SR & AT91C_PMC_MCKRDY));
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*AT91C_PIOA_PER = 0xFFFFFFFF; // enable pio on all pins
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*AT91C_PIOA_SODR = DISKLED; // led off
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#ifdef USB_PUP
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// disable usb d+/d- pullups if present
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*AT91C_PIOA_OER = USB_PUP;
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*AT91C_PIOA_PPUDR = USB_PUP;
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*AT91C_PIOA_SODR = USB_PUP;
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#endif
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// enable joystick ports
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#ifdef JOY0
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*AT91C_PIOA_PPUER = JOY0;
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#endif
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#ifdef JOY1
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*AT91C_PIOA_PPUER = JOY1;
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#endif
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#ifdef SD_WP
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// enable SD card signals
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*AT91C_PIOA_PPUER = SD_WP | SD_CD;
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#endif
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*AT91C_PIOA_SODR = MMC_SEL | FPGA0 | FPGA1 | FPGA2; // set output data register
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// output enable register
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*AT91C_PIOA_OER = DISKLED | MMC_SEL | FPGA0 | FPGA1 | FPGA2;
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// pull-up disable register
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*AT91C_PIOA_PPUDR = DISKLED | MMC_SEL | FPGA0 | FPGA1 | FPGA2;
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#ifdef XILINX_CCLK
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// xilinx interface
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*AT91C_PIOA_SODR = XILINX_CCLK | XILINX_DIN | XILINX_PROG_B;
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*AT91C_PIOA_OER = XILINX_CCLK | XILINX_DIN | XILINX_PROG_B;
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*AT91C_PIOA_PPUDR = XILINX_CCLK | XILINX_DIN | XILINX_PROG_B |
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XILINX_INIT_B | XILINX_DONE;
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#endif
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#ifdef ALTERA_DCLK
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// altera interface
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*AT91C_PIOA_SODR = ALTERA_DCLK | ALTERA_DATA0 | ALTERA_NCONFIG;
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*AT91C_PIOA_OER = ALTERA_DCLK | ALTERA_DATA0 | ALTERA_NCONFIG;
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*AT91C_PIOA_PPUDR = ALTERA_DCLK | ALTERA_DATA0 | ALTERA_NCONFIG |
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ALTERA_NSTATUS | ALTERA_DONE;
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#endif
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#ifdef MMC_CLKEN
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// MMC_CLKEN may be present
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// (but is not used anymore, so it's only setup passive)
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*AT91C_PIOA_SODR = MMC_CLKEN;
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*AT91C_PIOA_PPUDR = MMC_CLKEN;
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#endif
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#ifdef USB_SEL
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*AT91C_PIOA_SODR = USB_SEL;
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*AT91C_PIOA_OER = USB_SEL;
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*AT91C_PIOA_PPUDR = USB_SEL;
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#endif
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// Enable peripheral clock in the PMC
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA;
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}
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void hexdump(void *data, uint16_t size, uint16_t offset) {
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uint8_t i, b2c;
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uint16_t n=0;
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char *ptr = data;
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if(!size) return;
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while(size>0) {
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iprintf("%04x: ", n + offset);
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b2c = (size>16)?16:size;
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for(i=0;i<b2c;i++) iprintf("%02x ", 0xff&ptr[i]);
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iprintf(" ");
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for(i=0;i<(16-b2c);i++) iprintf(" ");
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for(i=0;i<b2c;i++) iprintf("%c", isprint(ptr[i])?ptr[i]:'.');
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iprintf("\n");
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ptr += b2c;
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size -= b2c;
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n += b2c;
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}
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}
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// A buffer of 256 bytes makes index handling pretty trivial
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volatile static unsigned char tx_buf[256];
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volatile static unsigned char tx_rptr, tx_wptr;
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volatile static unsigned char rx_buf[256];
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volatile static unsigned char rx_rptr, rx_wptr;
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void Usart0IrqHandler(void) {
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// Read USART status
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unsigned char status = AT91C_BASE_US0->US_CSR;
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// received something?
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if(status & AT91C_US_RXRDY) {
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// read byte from usart
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unsigned char c = AT91C_BASE_US0->US_RHR;
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// only store byte if rx buffer is not full
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if((unsigned char)(rx_wptr + 1) != rx_rptr) {
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// there's space in buffer: use it
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rx_buf[rx_wptr++] = c;
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}
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}
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// ready to transmit further bytes?
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if(status & AT91C_US_TXRDY) {
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// further bytes to send in buffer?
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if(tx_wptr != tx_rptr)
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// yes, simply send it and leave irq enabled
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AT91C_BASE_US0->US_THR = tx_buf[tx_rptr++];
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else
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// nothing else to send, disable interrupt
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AT91C_BASE_US0->US_IDR = AT91C_US_TXRDY;
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}
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}
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// check usart rx buffer for data
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void USART_Poll(void) {
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if(user_io_dip_switch1())
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xmodem_poll();
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while(rx_wptr != rx_rptr) {
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// this can a little be optimized by sending whole buffer parts
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// at once and not just single bytes. But that's probably not
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// worth the effort.
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char chr = rx_buf[rx_rptr++];
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if(user_io_dip_switch1()) {
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// if in debug mode use xmodem for file reception
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xmodem_rx_byte(chr);
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} else {
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iprintf("USART RX %d (%c)\n", chr, chr);
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// data available -> send via user_io to core
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user_io_serial_tx(&chr, 1);
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}
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}
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}
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void USART_Write(unsigned char c) {
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#if 0
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while(!(AT91C_BASE_US0->US_CSR & AT91C_US_TXRDY));
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AT91C_BASE_US0->US_THR = c;
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#else
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if((AT91C_BASE_US0->US_CSR & AT91C_US_TXRDY) && (tx_wptr == tx_rptr)) {
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// transmitter ready and buffer empty? -> send directly
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AT91C_BASE_US0->US_THR = c;
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} else {
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// transmitter is not ready: block until space in buffer
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while((unsigned char)(tx_wptr + 1) == tx_rptr);
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// there's space in buffer: use it
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tx_buf[tx_wptr++] = c;
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}
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AT91C_BASE_US0->US_IER = AT91C_US_TXRDY; // enable interrupt
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#endif
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}
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void USART_Init(unsigned long baudrate) {
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// Configure PA5 and PA6 for USART0 use
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AT91C_BASE_PIOA->PIO_PDR = AT91C_PA5_RXD0 | AT91C_PA6_TXD0;
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// Enable the peripheral clock in the PMC
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_US0;
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// Reset and disable receiver & transmitter
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AT91C_BASE_US0->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
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// Configure USART0 mode
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AT91C_BASE_US0->US_MR = AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS |
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AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT | AT91C_US_CHMODE_NORMAL;
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// Configure USART0 rate
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AT91C_BASE_US0->US_BRGR = MCLK / 16 / baudrate;
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// Enable receiver & transmitter
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AT91C_BASE_US0->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
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// tx buffer is initially empty
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tx_rptr = tx_wptr = 0;
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// and so is rx buffer
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rx_rptr = rx_wptr = 0;
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// Set the USART0 IRQ handler address in AIC Source
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AT91C_BASE_AIC->AIC_SVR[AT91C_ID_US0] = (unsigned int)Usart0IrqHandler;
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AT91C_BASE_AIC->AIC_IECR = (1<<AT91C_ID_US0);
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AT91C_BASE_US0->US_IER = AT91C_US_RXRDY; // enable rx interrupt
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}
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unsigned long CheckButton(void)
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{
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#ifdef BUTTON
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return((~*AT91C_PIOA_PDSR) & BUTTON);
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#else
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return user_io_menu_button();
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#endif
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}
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void timer0_c_irq_handler(void) {
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//* Acknowledge interrupt status
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unsigned int dummy = AT91C_BASE_TC0->TC_SR;
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ikbd_update_time();
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}
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void Timer_Init(void) {
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unsigned int dummy;
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//* Open timer0
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AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_TC0;
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//* Disable the clock and the interrupts
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS ;
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AT91C_BASE_TC0->TC_IDR = 0xFFFFFFFF ;
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//* Clear status bit
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dummy = AT91C_BASE_TC0->TC_SR;
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//* Set the Mode of the Timer Counter
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AT91C_BASE_TC0->TC_CMR = 0x04; // :1024
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//* Enable the clock
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN ;
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//* Open Timer 0 interrupt
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//* Disable the interrupt on the interrupt controller
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AT91C_BASE_AIC->AIC_IDCR = 1 << AT91C_ID_TC0;
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//* Save the interrupt handler routine pointer and the interrupt priority
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AT91C_BASE_AIC->AIC_SVR[AT91C_ID_TC0] = (unsigned int)timer0_c_irq_handler;
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//* Store the Source Mode Register
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AT91C_BASE_AIC->AIC_SMR[AT91C_ID_TC0] = 1 | AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL;
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//* Clear the interrupt on the interrupt controller
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AT91C_BASE_AIC->AIC_ICCR = 1 << AT91C_ID_TC0;
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AT91C_BASE_TC0->TC_IER = AT91C_TC_CPCS; // IRQ enable CPC
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AT91C_BASE_AIC->AIC_IECR = 1 << AT91C_ID_TC0;
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//* Start timer0
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AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG ;
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*AT91C_PITC_PIMR = AT91C_PITC_PITEN | ((MCLK / 16 / 1000 - 1) & AT91C_PITC_PIV); // counting period 1ms
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}
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// 12 bits accuracy at 1ms = 4096 ms
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unsigned long GetTimer(unsigned long offset)
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{
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unsigned long systimer = (*AT91C_PITC_PIIR & AT91C_PITC_PICNT);
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systimer += offset << 20;
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return (systimer); // valid bits [31:20]
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}
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unsigned long CheckTimer(unsigned long time)
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{
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unsigned long systimer = (*AT91C_PITC_PIIR & AT91C_PITC_PICNT);
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time -= systimer;
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return(time > (1UL << 31));
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}
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void WaitTimer(unsigned long time)
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{
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time = GetTimer(time);
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while (!CheckTimer(time));
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}
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void TIMER_wait(unsigned long ms) {
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WaitTimer(ms);
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}
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char mmc_inserted() {
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return !(*AT91C_PIOA_PDSR & SD_CD);
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}
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char mmc_write_protected() {
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return (*AT91C_PIOA_PDSR & SD_WP);
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}
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