LOCATE COMP "clk" SITE "A9";
IOBUF  PORT "clk" PULLMODE=NONE IO_TYPE=LVCMOS33;
FREQUENCY PORT "clk" 48.000 MHZ;

LOCATE COMP "r" SITE "K4";
LOCATE COMP "g" SITE "M3";
LOCATE COMP "b" SITE "J3";

IOBUF PORT "r" IO_TYPE=LVCMOS33;
IOBUF PORT "g" IO_TYPE=LVCMOS33;
IOBUF PORT "b" IO_TYPE=LVCMOS33;

LOCATE COMP "btn" SITE "J17";  # BTN_PWRn (inverted logic)
IOBUF PORT "btn" PULLMODE=UP IO_TYPE=LVCMOS33;

LOCATE COMP "tx" SITE "M18"; # FPGA serial output
IOBUF PORT "tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
