LOCATE COMP "clk" SITE "G2";
IOBUF  PORT "clk" PULLMODE=NONE IO_TYPE=LVCMOS33;
FREQUENCY PORT "clk" 25.000 MHZ;
LOCATE COMP "q" SITE "B2";
IOBUF  PORT "q" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;

LOCATE COMP "btn0" SITE "D6";  # BTN_PWRn (inverted logic)
IOBUF PORT "btn0" PULLMODE=UP IO_TYPE=LVCMOS33;

LOCATE COMP "wifi_gpio0" SITE "L2";
IOBUF  PORT "wifi_gpio0" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;

LOCATE COMP "uart_txd" SITE "L4"; # FPGA transmits to ftdi
IOBUF PORT "uart_txd" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
