From 04037c435476601c66b03309e30ba378442cc10c Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Wed, 30 Oct 2019 08:25:31 +0100 Subject: [PATCH] Split out RF to separate module --- rtl/{serv_mpram.v => serv_rf_2bit.v} | 78 +++++++------------------ rtl/serv_rf_if.v | 86 ++++++++++++++++++++++++++++ rtl/serv_top.v | 45 +++++++++++++-- serv.core | 4 +- 4 files changed, 149 insertions(+), 64 deletions(-) rename rtl/{serv_mpram.v => serv_rf_2bit.v} (51%) create mode 100644 rtl/serv_rf_if.v diff --git a/rtl/serv_mpram.v b/rtl/serv_rf_2bit.v similarity index 51% rename from rtl/serv_mpram.v rename to rtl/serv_rf_2bit.v index df85138..36a7a50 100644 --- a/rtl/serv_mpram.v +++ b/rtl/serv_rf_2bit.v @@ -1,36 +1,22 @@ `default_nettype none -module serv_mpram +module serv_rf_2bit ( input wire i_clk, input wire i_rst, - input wire i_run, - //Trap interface - input wire i_trap, - input wire i_mret, - input wire i_mepc, - input wire i_mtval, - output wire o_csr_pc, - //CSR interface - input wire i_csr_en, - input wire [1:0] i_csr_addr, - input wire i_csr, - output wire o_csr, - //RD write port - input wire i_rd_wen, - input wire [4:0] i_rd_waddr, - input wire i_rd, - input wire i_wreq, input wire i_rreq, output reg o_rgnt, - //RS1 read port - input wire [4:0] i_rs1_raddr, - output wire o_rs1, - //RS2 read port - input wire [4:0] i_rs2_raddr, - output wire o_rs2); + input wire [5:0] i_wreg0, + input wire [5:0] i_wreg1, + input wire i_wen0, + input wire i_wen1, + input wire i_wdata0, + input wire i_wdata1, + input wire [5:0] i_rreg0, + input wire [5:0] i_rreg1, + output wire o_rdata0, + output wire o_rdata1); -`include "serv_params.vh" /* ********** Write side *********** @@ -42,29 +28,16 @@ module serv_mpram wire [3:0] wslot = wcnt[4:1]; wire wport = wcnt[0]; - wire wdata0 = i_trap ? i_mtval : i_rd; - wire wdata1 = i_trap ? i_mepc : i_csr; reg wdata0_r; reg wdata1_r; reg wdata1_2r; wire [1:0] wdata = !wport ? - {wdata0 , wdata0_r} : + {i_wdata0, wdata0_r} : {wdata1_r, wdata1_2r}; - //port 0 rd mtval - //port 1 csr mepc - //mepc 100010 - //mtval 100011 - //csr 1000xx - //rd 0xxxxx - wire [5:0] wreg0 = i_trap ? {4'b1000,CSR_MTVAL} : {1'b0,i_rd_waddr}; - wire [5:0] wreg1 = i_trap ? {4'b1000,CSR_MEPC} : {4'b1000,i_csr_addr}; - wire [5:0] wreg = wport ? wreg1 : wreg0; + wire [5:0] wreg = wport ? i_wreg1 : i_wreg0; wire [9:0] waddr = {wreg, wslot}; - wire wen0 = i_trap | (i_rd_wen & i_run); - wire wen1 = i_trap | i_csr_en; - wire wen = wgo & (wport ? wen1_r : wen0_r); reg wreq_r; @@ -73,11 +46,11 @@ module serv_mpram reg wen1_r; always @(posedge i_clk) begin - wen0_r <= wen0; - wen1_r <= wen1; + wen0_r <= i_wen0; + wen1_r <= i_wen1; wreq_r <= i_wreq; - wdata0_r <= wdata0; - wdata1_r <= wdata1; + wdata0_r <= i_wdata0; + wdata1_r <= i_wdata1; wdata1_2r <= wdata1_r; if (wgo) @@ -97,32 +70,21 @@ module serv_mpram ********** Read side *********** */ - //0 : RS1 - //1 : RS2 / CSR reg [4:0] rcnt; wire [3:0] rslot = rcnt[4:1]; wire rport = rcnt[0]; - wire [5:0] rreg0 = {1'b0, i_rs1_raddr}; - wire [5:0] rreg1 = - i_trap ? {4'b1000, CSR_MTVEC} : - i_mret ? {4'b1000, CSR_MEPC} : - i_csr_en ? {4'b1000, i_csr_addr} : - {1'b0,i_rs2_raddr}; - wire [5:0] rreg = rport ? rreg1 : rreg0; + wire [5:0] rreg = rport ? i_rreg1 : i_rreg0; wire [9:0] raddr = {rreg, rslot}; reg [1:0] rdata; reg [1:0] rdata0; reg rdata1; - assign o_rs1 = !rport ? rdata0[0] : rdata0[1]; - assign o_rs2 = rport ? rdata1 : rdata[0]; - - assign o_csr = o_rs2 & i_csr_en; - assign o_csr_pc = o_rs2; + assign o_rdata0 = !rport ? rdata0[0] : rdata0[1]; + assign o_rdata1 = rport ? rdata1 : rdata[0]; reg rreq_r; diff --git a/rtl/serv_rf_if.v b/rtl/serv_rf_if.v new file mode 100644 index 0000000..89c7e7a --- /dev/null +++ b/rtl/serv_rf_if.v @@ -0,0 +1,86 @@ +`default_nettype none +module serv_rf_if + ( + input wire i_clk, + input wire i_rst, + + //RF Interface + output wire [5:0] o_wreg0, + output wire [5:0] o_wreg1, + output wire o_wen0, + output wire o_wen1, + output wire o_wdata0, + output wire o_wdata1, + output wire [5:0] o_rreg0, + output wire [5:0] o_rreg1, + input wire i_rdata0, + input wire i_rdata1, + + input wire i_run, + //Trap interface + input wire i_trap, + input wire i_mret, + input wire i_mepc, + input wire i_mtval, + output wire o_csr_pc, + //CSR interface + input wire i_csr_en, + input wire [1:0] i_csr_addr, + input wire i_csr, + output wire o_csr, + //RD write port + input wire i_rd_wen, + input wire [4:0] i_rd_waddr, + input wire i_rd, + + //RS1 read port + input wire [4:0] i_rs1_raddr, + output wire o_rs1, + //RS2 read port + input wire [4:0] i_rs2_raddr, + output wire o_rs2); + +`include "serv_params.vh" + + /* + ********** Write side *********** + */ + + assign o_wdata0 = i_trap ? i_mtval : i_rd; + assign o_wdata1 = i_trap ? i_mepc : i_csr; + + //port 0 rd mtval + //port 1 csr mepc + //mepc 100010 + //mtval 100011 + //csr 1000xx + //rd 0xxxxx + assign o_wreg0 = i_trap ? {4'b1000,CSR_MTVAL} : {1'b0,i_rd_waddr}; + assign o_wreg1 = i_trap ? {4'b1000,CSR_MEPC} : {4'b1000,i_csr_addr}; + + assign o_wen0 = i_trap | (i_rd_wen & i_run); + assign o_wen1 = i_trap | i_csr_en; + + /* + ********** Read side *********** + */ + + //0 : RS1 + //1 : RS2 / CSR + + + assign o_rreg0 = {1'b0, i_rs1_raddr}; + assign o_rreg1 = + i_trap ? {4'b1000, CSR_MTVEC} : + i_mret ? {4'b1000, CSR_MEPC} : + i_csr_en ? {4'b1000, i_csr_addr} : + {1'b0,i_rs2_raddr}; + + assign o_rs1 = i_rdata0; + assign o_rs2 = i_rdata1; + assign o_csr = i_rdata1 & i_csr_en; + assign o_csr_pc = i_rdata1; + + + +endmodule diff --git a/rtl/serv_top.v b/rtl/serv_top.v index 09ec10d..192da74 100644 --- a/rtl/serv_top.v +++ b/rtl/serv_top.v @@ -125,6 +125,17 @@ module serv_top wire [1:0] csr_addr; wire csr_pc; + wire [5:0] wreg0; + wire [5:0] wreg1; + wire wen0; + wire wen1; + wire wdata0; + wire wdata1; + wire [5:0] rreg0; + wire [5:0] rreg1; + wire rdata0; + wire rdata1; + parameter RESET_PC = 32'd8; wire new_irq; @@ -312,10 +323,21 @@ module serv_top wire csr_in; wire rf_csr_out; - serv_mpram regfile + serv_rf_if rf_if ( .i_clk (clk), .i_rst (i_rst), + .o_wreg0 (wreg0), + .o_wreg1 (wreg1), + .o_wen0 (wen0), + .o_wen1 (wen1), + .o_wdata0 (wdata0), + .o_wdata1 (wdata1), + .o_rreg0 (rreg0), + .o_rreg1 (rreg1), + .i_rdata0 (rdata0), + .i_rdata1 (rdata1), + .i_run (run), //Trap interface .i_trap (trap), @@ -332,18 +354,33 @@ module serv_top .i_rd_waddr (rd_addr), .i_rd (rd), - .i_rreq (rf_rreq), - .i_wreq (rf_wreq), - .o_rgnt (rf_ready), //RS1 read port .i_rs1_raddr (rs1_addr), .o_rs1 (rs1), //RS2 read port .i_rs2_raddr (rs2_addr), .o_rs2 (rs2), + //CSR read port .o_csr (rf_csr_out)); + serv_rf_2bit rf + (.i_clk (clk), + .i_rst (i_rst), + .i_wreq (rf_wreq), + .i_rreq (rf_rreq), + .o_rgnt (rf_ready), + .i_wreg0 (wreg0), + .i_wreg1 (wreg1), + .i_wen0 (wen0), + .i_wen1 (wen1), + .i_wdata0 (wdata0), + .i_wdata1 (wdata1), + .i_rreg0 (rreg0), + .i_rreg1 (rreg1), + .o_rdata0 (rdata0), + .o_rdata1 (rdata1)); + serv_mem_if mem_if ( .i_clk (clk), diff --git a/serv.core b/serv.core index f37b934..2c8b902 100644 --- a/serv.core +++ b/serv.core @@ -16,8 +16,8 @@ filesets: - rtl/serv_ctrl.v - rtl/serv_decode.v - rtl/serv_mem_if.v - - rtl/serv_regfile.v - - rtl/serv_mpram.v + - rtl/serv_rf_if.v + - rtl/serv_rf_2bit.v - rtl/serv_state.v - rtl/serv_top.v file_type : verilogSource