diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 93fb70d..fc823b7 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -7,68 +7,58 @@ jobs:
     name: RISC-V Compliance Test
     runs-on: ubuntu-20.04
 
-    strategy:
-      fail-fast: false
-      matrix:
-        compressed: [0, 1]
-        csr: [0, 1]
-        mdu: [0, 1]
-        exclude:
-          # compressed requires csr for the cebreak test
-          - compressed: 1
-            csr : 0
-        include:
-          - mdu: 1
-            mduflag: "--flag=mdu"
     steps:
     - uses: actions/checkout@v2
       with:
         path: serv
 
-    - name: install fusesoc, verilator and gcc
+    - name: install fusesoc, verilator, gcc and riscof
       run: |
         sudo apt-get install -y python3-setuptools verilator gcc-riscv64-unknown-elf
         pip3 install fusesoc
-
-    - name: set SERV directory
-      run: echo "SERV=$GITHUB_WORKSPACE/serv" >> $GITHUB_ENV
+        pip3 install git+https://github.com/riscv/riscof.git
+    
+    - name: set root and SERV directory
+      run: |
+        echo "SERV=$GITHUB_WORKSPACE/serv" >> $GITHUB_ENV
+        echo "WORKSPACE=$GITHUB_WORKSPACE/" >> $GITHUB_ENV
 
     - name: setup workspace
       run: fusesoc library add serv $SERV
-
-    - name: Add MDU core as a library
-      run: fusesoc library add mdu https://github.com/zeeshanrafique23/mdu
-
-    - name: build servant
-      run: fusesoc run --target=verilator_tb ${{ matrix.mduflag }} --build --build-root=servant_x servant --memsize=8388608 --align=1 --compressed=${{ matrix.compressed }} --with_csr=${{ matrix.csr }}
-
-    - name: download riscv-arch-test version 2.7.4
-      run: git clone https://github.com/riscv-non-isa/riscv-arch-test.git --branch 2.7.4
-
-    - name: run RV32 I compliance tests
+    
+    - name: Update submodule to add arch-tests
       run: |
-        cd $GITHUB_WORKSPACE/riscv-arch-test
-        make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=I TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
+        cd $SERV
+        git submodule init
+        git submodule update
 
-    - if: ${{ matrix.compressed }}
-      name: run RV32 C compliance tests
+    - name: Setup SAIL-RISCV Model
       run: |
-        cd $GITHUB_WORKSPACE/riscv-arch-test
-        make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=C TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
-
-    - if: ${{ matrix.mdu }}
-      name: run RV32 M compliance tests
+        tar -xzf $SERV/verif/bin/sail-riscv.tar.gz
+        echo $GITHUB_WORKSPACE/sail-riscv >> $GITHUB_PATH
+    
+    - name: Run RV32I compliance tests
       run: |
-        cd $GITHUB_WORKSPACE/riscv-arch-test
-        make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=M TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
-
-    - name: run RV32 Zifencei compliance tests
+        cd $SERV/verif
+        riscof run --config=config.ini --suite=riscv-arch-test/riscv-test-suite/rv32i_m/I --env=riscv-arch-test/riscv-test-suite/env --no-browser
+    
+    - name: Run RV32IM compliance tests
       run: |
-        cd $GITHUB_WORKSPACE/riscv-arch-test
-        make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=Zifencei TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
-
-    - if: ${{ matrix.csr }}
-      name: run RV32 privilege compliance tests
+        cd $SERV/verif
+        riscof run --config=config.ini --suite=riscv-arch-test/riscv-test-suite/rv32i_m/M --env=riscv-arch-test/riscv-test-suite/env --no-browser
+    
+    - name: Run RV32IC compliance tests
       run: |
-        cd $GITHUB_WORKSPACE/riscv-arch-test
-        make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=privilege TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
+        cd $SERV/verif
+        riscof run --config=config.ini --suite=riscv-arch-test/riscv-test-suite/rv32i_m/C --env=riscv-arch-test/riscv-test-suite/env --no-browser
+    
+    - name: Run RV32I Zifencei compliance tests
+      run: |
+        cd $SERV/verif
+        riscof run --config=config.ini --suite=riscv-arch-test/riscv-test-suite/rv32i_m/Zifencei --env=riscv-arch-test/riscv-test-suite/env --no-browser
+    
+    - name: Run RV32I Privilege compliance tests
+      run: |
+        cd $SERV/verif
+        riscof run --config=config.ini --suite=riscv-arch-test/riscv-test-suite/rv32i_m/privilege --env=riscv-arch-test/riscv-test-suite/env --no-browser
+    
\ No newline at end of file