github.com/olofk.serv
1
0
Fork 0
mirror of https://github.com/olofk/serv.git synced 2026-04-27 12:48:42 +00:00
Code Issues Releases Wiki Activity

Cleanup

Browse Source
This commit is contained in:
Olof Kindgren
2018-11-21 13:22:55 +01:00
parent 9df2a0060b
commit 079d973969
11 changed files with 1 additions and 18814 deletions
Download Patch File Download Diff File Expand all files Collapse all files

70
bench/serv_alu_tb.v
View File

@@ -1,70 +0,0 @@
`default_nettype none
module serv_alu_tb;
reg clk = 1'b1;
reg go;
reg instr;
reg jal;
wire [31:0] pc_data;
wire pc_valid;
reg pc_ready = 1'b1;
wire rd;
wire rd_valid;
wire done;
reg reg11;
reg [8:0] reg2012;
wire reg2012_en;
always #5 clk <= !clk;
vlog_tb_utils vtu();
serv_ctrl dut
(
.clk (clk),
.i_go (go),
.i_instr (instr),
.i_jal (jal),
.i_reg11 (reg11),
.i_reg2012 (reg2012[0]),
.o_reg2012_en (reg2012_en),
.o_rd (rd),
.o_rd_valid (rd_valid),
.o_pc_data (pc_data),
.o_pc_valid (pc_valid),
.i_pc_ready (pc_ready));
reg [31:0] instruction;
integer idx;
initial begin
instruction = 32'h3d80006f;
reg11 = instruction[20];
reg2012 = {instruction[31],instruction[19:12]};
for (idx=0;idx < 31;idx=idx+1) begin
go <= (idx == 19); //Check this
instr <= instruction[idx];
jal <= (idx > 7);
if (reg2012_en) reg2012 <= (reg2012 >> 1);
@(posedge clk);
end
while (!done)
@(posedge clk);
end // initial begin
reg [31:0] rd_word;
always @(posedge clk) begin
if (rd_valid)
rd_word = {rd, rd_word[31:1]};
if (pc_valid & pc_ready) begin
$display("New PC is %08x", pc_data);
$display("RD is %08x", rd_word);
end
end
endmodule

86
bench/serv_ctrl_tb.v
View File

@@ -1,86 +0,0 @@
`default_nettype none
module serv_ctrl_tb;
reg clk = 1'b1;
reg go;
wire en;
wire jump;
wire [31:0] pc_data;
wire pc_valid;
reg pc_ready = 1'b1;
wire rd;
wire rd_valid;
wire done;
reg reg11;
reg [8:0] reg2012;
wire reg2012_en;
always #5 clk <= !clk;
vlog_tb_utils vtu();
serv_decode decode
(
.clk (clk),
.i_go (go),
.i_instr (instruction),
.o_ctrl_jump (jump),
.o_ctrl_en (en),
.o_imm (offset),
.o_rd_from_ctrl ());
serv_ctrl
#(.RESET_PC (32'h464))
dut
(
.clk (clk),
.i_en (en),
.i_jump (jump),
.i_offset (offset),
.o_rd (rd),
.o_i_dat (pc_data),
.o_pc_valid (pc_valid),
.i_pc_ready (pc_ready));
reg [31:0] instruction;
integer idx;
reg [20:0] offset;
initial begin
instruction = 32'h3d80006f;
//instruction = 32'h0080706f;
offset = {instruction[31],
instruction[19:12],
instruction[20],
instruction[30:21],1'b0};
$display("Reconstructured offset %08x", offset);
en <= 1'b1;
for (idx=0;idx < 31;idx=idx+1) begin
go <= (idx == 20); //Check this
instr <= instruction[idx];
jal <= (idx > 7);
if (reg2012_en) reg2012 <= (reg2012 >> 1);
@(posedge clk);
end
while (!done)
@(posedge clk);
end // initial begin
reg [31:0] rd_word;
always @(posedge clk) begin
if (rd_valid)
rd_word = {rd, rd_word[31:1]};
if (pc_valid & pc_ready) begin
$display("New PC is %08x", pc_data);
$display("RD is %08x", rd_word);
end
end
endmodule

55
bench/serv_decode_tb.v
View File

@@ -1,55 +0,0 @@
`default_nettype none
module serv_decode_tb;
reg clk = 1'b1;
reg [31:0] i_rd_dat = 32'd0;
reg i_rd_vld = 1'b0;
wire i_rd_rdy;
wire ctrl_en;
wire ctrl_jump;
wire [4:0] rd_addr;
wire [4:0] rs1_addr;
wire [4:0] rs2_addr;
wire imm;
wire offset_source;
wire [1:0] rd_source;
reg [31:0] tb_imm;
always #5 clk <= !clk;
vlog_tb_utils vtu();
serv_decode decode
(
.clk (clk),
.i_i_rd_dat (i_rd_dat),
.i_i_rd_vld (i_rd_vld),
.o_i_rd_rdy (i_rd_rdy),
.o_ctrl_en (ctrl_en),
.o_ctrl_jump (ctrl_jump),
.o_rf_rd_addr (rd_addr),
.o_rf_rs1_addr (rs1_addr),
.o_rf_rs2_addr (rs2_addr),
.o_imm (imm),
.o_offset_source (offset_source),
.o_rd_source (rd_source));
initial begin
@(posedge clk);
i_rd_dat <= 32'h3d80006f;
i_rd_vld <= 1'b1;
@(posedge clk);
@(posedge i_rd_rdy);
@(posedge clk);
$display("imm = %08x", tb_imm);
$finish;
end
always @(posedge clk) begin
if (ctrl_en)
tb_imm <= {imm, tb_imm[31:1]};
end
endmodule