Fix bugs and missing resets to pass formal

2026-02-07 08:17:04 +00:00 · 2018-12-11 22:05:32 +01:00
parent af1d4da8bf
commit 09bb05071e
9 changed files with 57 additions and 22 deletions
--- a/rtl/ser_shift.v
+++ b/rtl/ser_shift.v
@@ -2,6 +2,7 @@
 module ser_shift
  (
   input wire 	    i_clk,
+   input wire 	    i_rst,
   input wire 	    i_load,
   input wire [4:0] i_shamt,
   input wire 	    i_signed,
@@ -17,6 +18,7 @@ module ser_shift

   shift_reg #(.LEN (32)) sh_reg
     (.clk (i_clk),
+      .i_rst (i_rst),
      .i_en (i_load),
      .i_d  (i_d),
      .o_q  (shiftreg[0]),