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Add support for setting memory contents during synthesis

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Olof Kindgren
2018-11-26 09:49:08 +01:00
parent e1f5bcc4f3
commit 12039dec0e
9 changed files with 2159 additions and 5 deletions
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bench/serv_wrapper.v
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@@ -4,8 +4,7 @@ module serv_wrapper
input wire wb_clk,
output wire q);
parameter memfile = "helloservice4000.hex";
// parameter memfile = "bitbang.hex";
parameter memfile = "zephyr_hello.hex";
reg [4:0] rst_reg = 5'b11111;