Add support for setting memory contents during synthesis

2026-02-09 17:21:00 +00:00 · 2018-11-26 09:49:08 +01:00
parent e1f5bcc4f3
commit 12039dec0e
9 changed files with 2159 additions and 5 deletions
--- a/rtl/serv_decode.v
+++ b/rtl/serv_decode.v
@@ -78,7 +78,6 @@ module serv_decode
   wire      running;
   wire      mem_op;
   wire      shift_op;
-   wire      csr_op;
   wire      slt_op;
   wire      branch_op;
   wire      e_op;