mirror of
https://github.com/olofk/serv.git
synced 2026-01-13 15:17:25 +00:00
Rewrite RF and state machine
Big patch, but would take more work to split it up
This commit is contained in:
Olof Kindgren
parent
8481fb46a1
commit
126937f16a
@ -105,7 +105,7 @@ module serv_alu
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assign o_rd = (i_rd_sel == ALU_RESULT_ADD) ? result_add :
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(i_rd_sel == ALU_RESULT_SR) ? result_sh :
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(i_rd_sel == ALU_RESULT_LT) ? result_lt_r :
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(i_rd_sel == ALU_RESULT_LT) ? result_lt_r & plus_1:
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(i_rd_sel == ALU_RESULT_BOOL) ? result_bool : 1'bx;
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@ -117,8 +117,6 @@ module serv_alu
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eq_r <= result_eq;
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end else begin
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eq_r <= 1'b1;
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if (result_lt_r)
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result_lt_r <= 1'b0;
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end
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en_r <= i_en;
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end
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172
rtl/serv_mpram.v
172
rtl/serv_mpram.v
@ -6,6 +6,7 @@ module serv_mpram
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input wire i_run,
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//Trap interface
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input wire i_trap,
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input wire i_mret,
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input wire i_mepc,
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input wire i_mtval,
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output wire o_csr_pc,
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@ -19,6 +20,7 @@ module serv_mpram
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input wire [4:0] i_rd_waddr,
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input wire i_rd,
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input wire i_wreq,
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input wire i_rreq,
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output reg o_rgnt,
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//RS1 read port
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@ -30,29 +32,24 @@ module serv_mpram
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`include "serv_params.vh"
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wire [8:0] waddr;
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/*
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********** Write side ***********
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*/
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reg [4:0] wdata0;
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reg [5:0] wdata1;
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reg [4:0] wcnt;
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reg wgo;
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wire [3:0] wdata;
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wire [3:0] wslot = wcnt[4:1];
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wire wport = wcnt[0];
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wire wen;
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reg [1:0] wen_r;
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reg [3:0] wcnt_lo;
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reg [2:0] wcnt_hi;
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reg wgo_r;
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reg trap_r;
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reg trap_2r;
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reg trap_3r;
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assign wdata = wcnt_lo[0] ? wdata0[3:0] : wdata1[3:0];
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assign wen = !wgo_r & |(wen_r & wcnt_lo[1:0]);
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reg [4:0] rd_waddr;
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wire wdata0 = i_trap ? i_mtval : i_rd;
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wire wdata1 = i_trap ? i_mepc : i_csr;
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reg wdata0_r;
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reg wdata1_r;
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reg wdata1_2r;
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wire [1:0] wdata = !wport ?
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{wdata0 , wdata0_r} :
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{wdata1_r, wdata1_2r};
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//port 0 rd mtval
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//port 1 csr mepc
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@ -60,105 +57,90 @@ module serv_mpram
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//mtval 100011
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//csr 1000xx
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//rd 0xxxxx
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wire [5:0] waddr0 = trap_3r ? {4'b1000,CSR_MTVAL} : {1'b0,rd_waddr};
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wire [5:0] waddr1 = trap_3r ? {4'b1000,CSR_MEPC} : {4'b1000,i_csr_addr};
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wire [5:0] wreg0 = i_trap ? {4'b1000,CSR_MTVAL} : {1'b0,i_rd_waddr};
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wire [5:0] wreg1 = i_trap ? {4'b1000,CSR_MEPC} : {4'b1000,i_csr_addr};
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wire [5:0] wreg = wport ? wreg1 : wreg0;
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wire [9:0] waddr = {wreg, wslot};
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assign waddr[8:3] = wcnt_lo[0] ? waddr0 : waddr1;
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wire wen = wgo & (i_trap | (wport ? i_csr_en : i_rd_wen & run_r));
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// assign waddr[8] = wcnt_lo[1] | i_trap;
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// assign waddr[7:5] = (wcnt_lo[1] | i_trap) ? 3'b000 : rd_waddr[4:2];
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// assign waddr[4:3] = wcnt_lo[0] ? (i_trap ? CSR_MTVAL : rd_waddr[1:0]) :
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// (i_trap ? CSR_MEPC : i_csr_addr);
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assign waddr[2:0] = wcnt_hi;
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wire wgo = !(|wcnt_lo) & ((i_run & (i_rd_wen | i_csr_en)) | i_trap);
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reg wreq_r;
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reg run_r;
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always @(posedge i_clk) begin
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trap_r <= i_trap;
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trap_2r <= trap_r;
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trap_3r <= trap_2r;
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wreq_r <= i_wreq | o_rgnt;
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wdata0_r <= wdata0;
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wdata1_r <= wdata1;
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wdata1_2r <= wdata1_r;
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run_r <= i_run;
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if (wgo)
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wcnt <= wcnt+5'd1;
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if (wreq_r)
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wgo <= 1'b1;
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if (wcnt == 5'b11111)
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wgo <= 1'b0;
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if (wgo) begin
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wgo_r <= 1'b1;
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wen_r <= {(i_run & i_csr_en)|i_trap,(i_rd_wen & i_run)|i_trap};
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rd_waddr <= i_rd_waddr;
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end
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wdata0 <= {i_trap ? i_mtval : i_rd ,wdata0[4:1]};
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wdata1 <= {i_trap ? i_mepc : i_csr,wdata1[5:1]};
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wcnt_lo <= {wcnt_lo[2:0],wcnt_lo[3] | wgo};
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if (wcnt_lo[3]) begin
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wcnt_hi <= wcnt_hi + 1;
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if (wcnt_hi == 3'd7) begin
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wgo_r <= !wgo_r;
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wcnt_lo[0] <= wgo_r;
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wcnt_hi <= wcnt_hi + {2'b00,wgo_r};
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end
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end
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if (i_rst) begin
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wgo_r <= 1'b0;
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wcnt_lo <= 4'd0;
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wcnt_hi <= 3'd7;
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wcnt <= 5'd0;
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end
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end
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/*
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********** Read side ***********
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*/
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//0 : RS1
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//1 : RS2
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//2 : CSR
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reg [2:0] rcnt_hi;
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reg [3:0] rcnt_lo;
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//1 : RS2 / CSR
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wire [8:0] raddr;
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reg [4:0] rcnt;
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wire [3:0] rslot = rcnt[4:1];
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wire rport = rcnt[0];
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reg [3:0] rdata;
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wire [5:0] rreg0 = {1'b0, i_rs1_raddr};
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wire [5:0] rreg1 =
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i_trap ? {4'b1000, CSR_MTVEC} :
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(i_csr_en | i_mret) ? {4'b1000, i_csr_addr} :
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{1'b0,i_rs2_raddr};
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wire [5:0] rreg = rport ? rreg1 : rreg0;
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wire [9:0] raddr = {rreg, rslot};
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reg [5:0] rdata0;
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reg [4:0] rdata1;
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reg [3:0] rdata2;
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//reg [3:0] rdata3;
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reg [1:0] rdata;
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reg [1:0] rdata0;
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reg rdata1;
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reg [2:0] rreq;
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assign o_rs1 = !rport ? rdata0[0] : rdata0[1];
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assign o_rs2 = rport ? rdata1 : rdata[0];
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assign o_csr = o_rs2 & i_csr_en;
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assign o_csr_pc = o_rs2;
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reg rreq_r;
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always @(posedge i_clk) begin
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{o_rgnt,rreq} <= {rreq[2:0],i_rreq};
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if (rcnt_lo[3])
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rcnt_hi <= rcnt_hi + 1;
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if (i_rreq) begin
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rcnt_lo <= 4'd1;
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rcnt_hi <= 3'd0;
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end else
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rcnt_lo <= {rcnt_lo[2:0],rcnt_lo[3]};
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rcnt <= rcnt+5'd1;
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if (i_rreq)
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rcnt <= 5'd0;
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rdata0[4:0] <= rdata0[5:1];
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rdata1[3:0] <= rdata1[4:1];
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rdata2[2:0] <= rdata2[3:1];
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//rdata3[2:0] <= rdata3[3:1];
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rreq_r <= i_rreq;
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o_rgnt <= rreq_r;
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if (rcnt_lo[1]) rdata0[5:2] <= rdata;
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if (rcnt_lo[2]) rdata1[4:1] <= rdata;
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if (rcnt_lo[3]) rdata2[3:0] <= rdata;
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//if (rcnt_lo[0]) rdata3[3:0] <= rdata;
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if (rport)
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rdata0 <= rdata;
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if (!rport)
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rdata1 <= rdata[1];
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if (i_rst) begin
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o_rgnt <= 1'b0;
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rreq <= 3'd0;
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rreq_r <= 1'b0;
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end
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end
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assign raddr[8] = rcnt_lo[2];
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assign raddr[7:5] = rcnt_lo[0] ? i_rs1_raddr[4:2] :
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rcnt_lo[1] ? i_rs2_raddr[4:2] : 3'd0;
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assign raddr[4:3] = rcnt_lo[0] ? i_rs1_raddr[1:0] :
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rcnt_lo[1] ? i_rs2_raddr[1:0] :
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i_trap ? CSR_MTVEC : i_csr_addr;
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assign raddr[2:0] = rcnt_hi;
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assign o_rs1 = rdata0[0];
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assign o_rs2 = rdata1[0];
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assign o_csr = rdata2[0] & i_csr_en;
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assign o_csr_pc = rdata2[0];
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reg [3:0] memory [0:511];
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reg [1:0] memory [0:1023];
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always @(posedge i_clk) begin
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if (wen)
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@ -176,8 +158,8 @@ module serv_mpram
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`ifdef SERV_CLEAR_RAM
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integer i;
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initial
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for (i=0;i<256;i=i+1)
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memory[i] = 4'd0;
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for (i=0;i<512;i=i+1)
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memory[i] = 2'd0;
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`endif
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endmodule
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@ -6,6 +6,7 @@ module serv_state
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input wire i_dbus_ack,
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input wire i_ibus_ack,
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output wire o_rf_rreq,
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output wire o_rf_wreq,
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input wire i_rf_ready,
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input wire i_take_branch,
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input wire i_branch_op,
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@ -32,7 +33,7 @@ module serv_state
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input wire i_mem_misalign,
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output reg [3:0] o_csr_mcause,
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output wire o_cnt_done,
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output reg o_bufreg_hold,
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output wire o_bufreg_hold,
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output wire o_csr_imm);
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localparam [1:0]
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@ -44,6 +45,7 @@ module serv_state
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reg [1:0] state;
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reg cnt_done;
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reg stage_two_req;
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wire cnt_en;
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wire running;
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@ -86,12 +88,22 @@ module serv_state
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assign o_dbus_cyc = (state == IDLE) & stage_two_pending & i_mem_op & !mem_misalign;
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assign o_rf_rreq = i_ibus_ack;
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wire trap_pending = (o_ctrl_jump & i_ctrl_misalign) | mem_misalign;
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//Prepare RF for reads when a new instruction is fetched
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// or when stage one caused an exception (rreq implies a write request too)
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assign o_rf_rreq = i_ibus_ack | (stage_two_req & trap_pending);
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//Prepare RF for writes when everything is ready to enter stage two
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assign o_rf_wreq = ((i_shift_op & i_alu_sh_done & stage_two_pending) | (i_mem_op & i_dbus_ack) | (stage_two_req & (i_slt_op | i_branch_op))) & !trap_pending;
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//Shift operations require bufreg to hold for one cycle between INIT and RUN before shifting
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assign o_bufreg_hold = !cnt_en & (stage_two_req | ~i_shift_op);
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always @(posedge i_clk) begin
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if (state == INIT)
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o_ctrl_jump <= i_take_branch;
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if (state == IDLE)
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if (o_ctrl_pc_en & cnt_done)
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o_ctrl_jump <= 1'b0;
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if (cnt_en)
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@ -102,41 +114,37 @@ module serv_state
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cnt_done <= (o_cnt[4:2] == 3'b111) & o_cnt_r[2];
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//Shift operations require bufreg to hold for one cycle before shifting
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o_bufreg_hold <= i_shift_op & cnt_done;
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//Need a strobe for the first cycle in the IDLE state after INIT
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stage_two_req <= cnt_done & (state == INIT);
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case (state)
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IDLE : begin
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if (i_rf_ready | i_dbus_ack) begin
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state <= RUN;
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if (two_stage_op & !stage_two_pending)
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state <= INIT;
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if (i_e_op | pending_irq)
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if (stage_two_pending) begin
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if (o_rf_wreq)
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state <= RUN;
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if (trap_pending & i_rf_ready)
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state <= TRAP;
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end else if (i_alu_sh_done & i_shift_op & stage_two_pending)
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state <= RUN;
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end
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end else begin
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if (i_rf_ready)
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if (i_e_op | pending_irq)
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state <= TRAP;
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else if (two_stage_op)
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state <= INIT;
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else
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state <= RUN;
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end
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end
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INIT : begin
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if (cnt_done)
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if (mem_misalign | (i_take_branch & i_ctrl_misalign))
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state <= TRAP;
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else if (i_mem_op | i_shift_op )
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state <= IDLE;
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else
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state <= RUN;
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end
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RUN : begin
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if (cnt_done)
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state <= IDLE;
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end
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TRAP : begin
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pending_irq <= 1'b0;
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if (cnt_done)
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state <= IDLE;
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end
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default : state <= IDLE;
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endcase
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if (cnt_done)
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state <= IDLE;
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o_cnt <= o_cnt + {4'd0,cnt_en};
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if (cnt_en)
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@ -99,6 +99,7 @@ module serv_top
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wire [1:0] alu_rd_sel;
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wire rf_rreq;
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wire rf_wreq;
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wire rf_ready;
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wire rs1;
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wire rs2;
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@ -144,6 +145,7 @@ module serv_top
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.i_dbus_ack (i_dbus_ack),
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.i_ibus_ack (i_ibus_ack),
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.o_rf_rreq (rf_rreq),
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.o_rf_wreq (rf_wreq),
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.i_rf_ready (rf_ready),
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.i_take_branch (take_branch),
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.i_branch_op (branch_op),
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@ -240,7 +242,7 @@ module serv_top
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.i_rst (i_rst),
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.i_cnt (cnt[4:2]),
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.i_cnt_r (cnt_r[1:0]),
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.i_en (!(bufreg_hold | o_dbus_cyc)),
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.i_en (!bufreg_hold),
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.i_init (init),
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.i_loop (bufreg_loop),
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.i_rs1 (rs1),
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@ -318,6 +320,7 @@ module serv_top
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.i_run (run),
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//Trap interface
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.i_trap (trap),
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.i_mret (mret),
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.i_mepc (o_ibus_adr[0]),
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.i_mtval ((mem_misalign & mem_op) ? bufreg_q : bad_pc),
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.o_csr_pc (csr_pc),
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@ -331,6 +334,7 @@ module serv_top
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.i_rd (rd),
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.i_rreq (rf_rreq),
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.i_wreq (rf_wreq),
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.o_rgnt (rf_ready),
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//RS1 read port
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.i_rs1_raddr (rs1_addr),
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